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| INSTRUCTION MANUAL nX-4/250/300 Core CMOS 4-BIT MICROCONTROLLER FIRST EDITION ISSUE DATE: Jun., 1997 nX-4/250/300 Core Instruction Manual Table of contents Table of Contents Introduction Chapter 1 - Architecture 1. OVERVIEW ....................................................................................................................1-1 2. CPU RESOURCES AND PROGRAMMING MODEL .....................................................1-1 2.1 Registers ....................................................................................................................1-3 2.1.1 Accumulator (A) ..................................................................................................1-4 2.1.2 Flag register .......................................................................................................1-4 2.1.2.1 Carry flag (C) ............................................................................................1-4 2.1.2.2 Zero flag (Z) ..............................................................................................1-4 2.1.2.3 G flag (G) ..................................................................................................1-4 2.1.3 Master interrupt enable flag (MIE) ......................................................................1-5 2.1.4 H register, L register, X register, Y register ........................................................1-5 2.1.5 Current bank register (CBR), extra bank register (EBR) ..................................... 1-6 2.1.6 RA register (RA3, RA2, RA1, RA0) ......................................................................1-7 2.1.7 Program counter (PC) .........................................................................................1-7 2.1.8 Stack pointer (SP, SPH/SPL) .............................................................................1-8 2.1.9 Register stack pointer (RSP) ..............................................................................1-9 2.2 Memory spaces .......................................................................................................1-10 2.2.1 Program memory space ...................................................................................1-10 2.2.2 Data memory space .........................................................................................1-13 2.2.2.1 SFR space ..............................................................................................1-14 2.2.3 External memory space .................................................................................... 1-15 2.3 Addressing modes ...................................................................................................1-16 2.3.1 Register addressing modes .............................................................................1-16 2.3.1.1 Register direct addressing mode ........................................................... 1-16 2.3.1.2 Bit direct addressing mode .................................................................... 1-17 2.3.1.3 Immediate addressing mode .................................................................1-17 2.3.2 Data memory addressing modes .....................................................................1-18 2.3.2.1 Direct addressing mode ......................................................................... 1-19 2.3.2.2 SFR bank internal direct addressing mode ........................................... 1-19 2.3.2.3 Current bank internal direct addressing mode ...................................... 1-20 2.3.2.4 HL register indirect addressing mode .................................................... 1-20 2.3.2.5 XY register indirect addressing mode .................................................... 1-21 2.3.2.6 Extra bank HL indirect addressing mode .............................................. 1-21 2.3.2.7 Extra band XY indirect addressing mode .............................................. 1-22 2.3.2.8 HL register indirect addressing mode with post increment ...............................................................................1-22 2.3.2.9 XY register indirect addressing mode with post-increment ...............................................................................1-23 2.3.2.10 Extra bank HL register indirect addressing mode with post-increment ...............................................................................1-23 2.3.2.11 Extra bank XY register indirect addressing mode with post-increment ...............................................................................1-24 1 nX-4/250/300 Core Instruction Manual Table of contents 2.3.2.12 Bit direct addressing mode .................................................................... 1-24 2.3.2.13 Bit indirect addressing mode .................................................................1-25 2.3.3 Addressing modes for program memory ......................................................... 1-26 2.3.3.1 64K word direct addressing mode ......................................................... 1-26 2.3.3.2 4K word page addressing mode ............................................................1-27 2.3.3.3 RA register indirect addressing mode ...................................................1-27 2.3.3.4 PC relative addressing mode .................................................................1-28 2.3.3.5 PC based addressing mode .................................................................. 1-29 2.3.4 Addressing mode for external memory ............................................................1-29 2.3.4.1 RA register indirect addressing mode ...................................................1-29 2.3.4.2 Direct addressing mode ......................................................................... 1-30 Chapter 2 - Instruction set 1. OVERVIEW ....................................................................................................................2-1 2. OPERAND EXPRESSION ..............................................................................................2-3 3. LIST OF INSTRUCTIONS ..............................................................................................2-5 4. INSTRUCTION DESCRIPTIONS .................................................................................2-33 2 nX-4/250/300 Core Instruction Manual Introduction Introduction This manual describes the instruction set of the nX-4/250 core and nX-4/300 core, which is designed for use as the CPU core for the original OKI CMOS 4-bit microcontroller. This manual is designed on the basis of the nX-4/250 core and nX-4/300 core basic architecture. The basic architecture of these constitutes the most important functional specifications of the nX4/250 core and nX-4/300 core. Depending on the model you are using the actual supported memory capacity may be a subset of the basic architecture. Please refer to the individual user's manual for such information. The following manuals related to the product line-up built around the nX-4/250 core and nX-4/300 core are available. Please refer to them for additional information. n MSM63XXX User's Manual Hardware description n ASM63KN Cross-assembler User's Manual Description of assembler operation and language specifications n EASE63XXX User's Manual Emulator hardware description n SID63K Operation Manual Debugger command description This manual consists of two chapters. Chapter 1 discusses the nX-4/250 core and nX-4/300 core basic architecture, beginning with explanations of the major resources used by the program, such as registers and memory, and then discussing addressing modes. explains the functions of each instruction, covering instruction function, their detailed action, and the instruction codes. Instruction descriptions are arranged in alphabetical order to serve as a reference. Chapter 2 0-1 Chapter 1 ARCHITECTURE This chapter describes the basic architecture of the nX-4/250 core and nX-4/300 core. The basic architecture is the most significant functional specification of the nX-4/250 core and nX-4/300. All microcontrollers using this core will have the same function as the basic architecture, or a subset thereof. This chapter covers the objectives of this document and its composition. nX-4/250/300 Core Instruction Manual Chapter 1 Architecture 1. OVERVIEW The nX-4/250 core and nX-4/300 core instruction set consist of 440/450 instructions. The memory spaces are divided into a 16-bit width program memory space, a 4-bit width data memory space, and external 8-bit width memory. The program counter save stack (call stack) for subroutine call or interruption and register save stack (register stack) are prepared separately from memory space. The nX-4/250 core is a downward version of the nX-4/300 core. The differences between them are shown below. Table 1-1 Differences between nX-4/250 Core and nX-4/300 Core Core nX-4/250 nX-4/300 MMOV instruction BMOV instruction FCLR FLAG instruction FSET FLAG instruction Not provided provided Not provided provided Not provided provided Not provided provided 2. CPU RESOURCES AND PROGRAMMING MODEL This section describes the configuration of the CPU resources used in programming, such as registers and memory, along with their roles. Figures 1-1 to 1-2 show the relationship between program memory space, external memory, data memory and registers. Figures 1-3 show the relationship between these memory spaces and stack registers. Program Memory External Memory 0FFFFH 0FFFFH Program Data or ROM Table Data or Melody Data PC Interrupt Area 0000H 16 Bits RA 0000H 8 Bits Fig. 1-1 Relationship between Program Memory, External Memory, and Registers 1-1 nX-4/250/300 Core Instruction Manual Chapter 1 Architecture Data Memory 0FFFH BANK15 RAM 0F00H CBR CBR EBR EBR 2FFH BANK2 RAM 200H 1FFH BANK1 Display Register 100H 0FFH BANK0 SFR 000H 4 Bits H X H X L Y L Y Fig. 1-2 Relationship between Data Memory and Registers Call Stack 32 Levels SPH SPL 16 Bits Register Stack 16 Levels RSP 16 Bits Fig. 1-3 Relationship between Stacks and Registers 1-2 nX-4/250/300 Core Instruction Manual Chapter 1 Architecture 2.1 Registers The nX-4/250 core and nX-4/300 core adopt a processing method that uses primarily accumulators and registers. The register set uses the programming model, with data memory addresses stored in the HL register, XY register, current bank register (CBR), extra bank register (EBR), and external memory and program memory addresses in the RA register. In addition registers are provided to control program flow, flags and memory. Figures 1-4 show register configurations. 3 A Accumulator 15 0 G C Z Flag Registers 0 PC Program Counter 15 RA3 12 11 RA2 87 RA1 43 RA0 0 RA Registers 3 RSP Register Stack Pointer 4 SPH 3 SPL 0 0 Stack Pointer 3 CBR Current Bank Register 3 EBR Extra Bank Register MIE Master Interrupt Enable Flag 0 7 X XY Register 0 7 H HL Register 43 Y 0 43 L 0 Fig. 1-4 Register Configuration 1-3 nX-4/250/300 Core Instruction Manual Chapter 1 Architecture 2.1.1 Accumulator (A) Accumulator (A) is a critical register for arithmetic operations. The accumulator is initialized to zero at reset. In the event that accumulator contents must be saved when an interrupt is generated or at other times, the PUSH HL instruction is used to save the value to the register stack. The register is restored with the POP HL instruction. 3 2 1 0 Fig. 1-5 Accumulator (A) 2.1.2 Flag registers The flag register consists of three flags: the carry flag (C), the zero flag (Z) and the G flag (G). In the event that flag register contents must be saved when an interrupt is generated or at other times, the PUSH HL instruction is used to save the value to the register stack. The register is restored with the POP HL instruction. G C Z Fig. 1-6 Flag Registers 2.1.2.1 Carry flag (C) The carry flag (C) is a 1-bit flag, and is used to load the carry for an additional instruction or the borrow for a subtraction instruction. The carry flag is initialized to zero at reset. 2.1.2.2 Zero flag (Z) The zero flag (Z) is a 1-bit flag, and is set to "1" when the content of the accumulator (A) is set to "0H". It is cleared to "0" when the content of the accumulator (A) is set to any value other than "0H". The zero flag is initialized to zero at reset. 2.1.2.3 G flag (G) The G flag is a 1-bit flag. This flag is set to "1" when the HL register, XY register, or RA register overflows as a result of execution of an increment instruction and is cleared to "0" when an overflow does not occur. The HL register or XY register is incremented when an indirect addressing instruction with post increment is executed or when an increment instruction is executed for the HL register or XY register. The RA register is incremented when an increment instruction is executed. 1-4 nX-4/250/300 Core Instruction Manual Chapter 1 Architecture 2.1.3 Master interrupt enable flag (MIE) The master interrupt enable flag (MIE) is the flag used to control enable/disable for maskable interrupts. When set to "1" maskable interrupts are enabled, and when cleared to "0" maskable interrupts are disabled. If a maskable interrupt is received, the MIE flag is cleared to "0", and then restored to "1" through the execution of the maskable interrupt return instruction (RTI instruction). Instruction execution in the maskable interrupt processing routine can set to the MIE flag to "1" to make possible multilevel interrupt processing. MIE flag set and clear are implemented with the "EI" and "DI" instructions, which are only used for MIE flag operations. The MIE flag is initialized to zero at reset. The MIE flag is allocated to address 0FFH of the special function register (SFR). 2.1.4 H register, L register, X register, Y register The H register, L register, X register and Y register are used as working registers during program processing. The H and L registers are used as a register pair in the data memory indirect addressing mode, as are the X and Y registers. All four registers are initialized to zero at reset. In the event that register contents must be saved when an interrupt is generated or at other times, the PUSH HL or PUSH XY instruction is used to save the value to the register stack. The register is restored with the POP HL or POP XY instruction. The H, L, X and Y registers are allocated to addresses 0F9H through 0FCH of the special function register (SFR). 3 2 H 1 03 2 L 1 0 HL Register Pair H Register 3 2 X X Register 1 03 L Register 2 Y Y Register 1 0 XY Register Pair Fig. 1-7 H, L, X, and Y Registers 1-5 nX-4/250/300 Core Instruction Manual Chapter 1 Architecture 2.1.5 Current bank register (CBR), extra bank register (EBR) The current bank register (CBR) and extra bank register (EBR) are used for data memory space bank specification. CBR and EBR are initialized to zero at reset. In the event that register contents must be saved when an interrupt is generated or at other times, the PUSH XY instruction is used to save the value to the register stack. The register is restored with the POP XY instruction. The CBR and EBR are allocated to addresses 0FDH through 0FEH of the special function register (SFR). 3 2 CBR Current Bank Register (CBR) 3 2 EBR Extra Bank Register (EBR) Fig. 1-8 Current Bank Register and Extra Bank Register CBR and EBR are used in combination with the HL and XY registers for indirect addressing of data memory. CBR is used in combination with the 8-bit data in the instruction code for direct addressing within the current bank. Fig. 1-9 indicates the register combinations used. 1 0 1 0 CBR CBR EBR EBR CBR A11 ~ A8 + + + + + H X H X L Y L Y Instruction code 8-bit data A7 ~ A4 A3 ~ A0 Fig. 1-9 Register Combinations A11 to A0 indicate data memory (max. 4K nibbles ) address. 1-6 nX-4/250/300 Core Instruction Manual Chapter 1 Architecture 2.1.6 RA register (RA3, RA2, RA1, RA0) THe RA registers are used for program memory indirect addressing (ROM table reference instruction) and external memory indirect addressing (external memory transfer instruction). Fig. 1-10 indicates the address configuration for the RA registers. RA3 A15 ~ A12 RA2 A11 ~ A8 RA1 A7 ~ A4 RA0 A3 ~ A0 Fig. 1-10 Address Configuration for Registers RA3 through RA0 When used for ROM table reference instructions, A15 through A0 indicate a maximum of 64K bytes of program memory addresses. When used for external memory transfer instructions, A15 through A0 indicate a maximum of 64K bytes of external memory addresses. RA3 through RA0 are allocated to addresses 0F2H through 0F5H of the special function register (SFR). The RA registers are initialized to zero at reset. 2.1.7 Program counter (PC) The program counter (PC) is the counter used to store the address of the program code to be executed next. The PC bit length is 16 bits , which means it can specify an address within 64K byte program memory space. The PC is increased immediately after the program code is fetched from program memory, and this repetition creates program flow. For a branch instruction the new program code address is set to the PC. The PC is initialized to zero at reset. When an interrupt is generated the execution restart address is automatically saved to the call stack. This value can be restored to the PC through the RTI instruction. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Fig. 1-11 Program Counter 1-7 nX-4/250/300 Core Instruction Manual Chapter 1 Architecture 2.1.8 Stack pointer (SP or SPH/SPL) The stack pointer (SP or SPH/SPL) is a pointer indicating the head address of the call stack, which is used for saving program counters at subroutine calls and interrupt. The stack pointer is a 5-bit up/down counter , counting up at stack save and down at stack restore. The call stack is 16 bits wide, and uses one level for PC save. It has a maximum of 32 levels. The stack ponter is initialized to zero at reset, and points to address "00H" in the call stack. The SPH/SPL are allocated to address "0F8H" and "0F7H", respectively, of the special function register (SFR). The stack pointer is a read-only register, and write is disabled. Figs. 1-12 indicate the relation between the stack pointer (SP) and the call stack. Call Stack 0FH 43 SPH 2 SPL 1 0 32 Levels Stack Pointer 0H 16 Bits Fig. 1-12 Relation between SPH/SPL and Call Stack 1-8 nX-4/250/300 Core Instruction Manual Chapter 1 Architecture 2.1.9 Register stack pointer (RSP) The register stack pointer (RSP) is a pointer indicating the address of the register stack, used for saving various registers. The RSP is a 4-bit up/down counter, counting up at stack save (PUSH instruction) and down at a stack restore (POP instruction). The register stack is 16 bits wide, and uses one level for register save. It has a maximum of 16 levels. The RSP is initialized to zero at reset, and points to address "0H" in the call stack. The RSP is allocated to address "0F6H" of the special function register (SFR). Fig. 1-13 indicates the relation between the RSP and the register stack. Register Stack 0FH 3 2 1 RSP Register Stack Pointer 00H 16 Bits 0 16 Levels Fig. 1-13 Relation between RSP and Register Stack The PUSH/POP instructions can be used to save various registers to the register stack, and restore them, as shown in Fig. 1-14. PUSH HL and POP HL instruction execution 15 -- 14 G 13 C 12 Z 11 10 A Register Stack PUSH XY and POP XY instruction execution 15 14 13 12 11 10 9 8 7 6 X Register Stack 5 4 3 2 Y 1 0 9 8 7 6 H 5 4 3 2 L 1 0 EBR CBR Fig. 1-14 Save/restore registers at PUSH/POP Instruction Execution 1-9 nX-4/250/300 Core Instruction Manual Chapter 1 Architecture 2.2 Memory spaces The nX-4/250 core and nX-4/300 core memory spaces each consist of program memory space, data memory space and external memory space. This section discusses the structures of these memory spaces. Note that the program counter save stack (call stack) used at subroutine calls or interrupts, the address save stack (melody stack) for melody output and the register save stack (register stack) are separate from the memory space. 2.2.1 Program memory space Program memory has a 16-bit data length with a 64 word capacity. The program memory space stores ROM data and melody data in addition to program data. Figs. 1-15 indicate the program memory configurations. 0FFFFH Program Data or ROM Table Data or Melody Data 65536 Words 00FFH Interrupt Area 0001H 0000H 16 Bits Instruction Execution Start Address Fig. 1-15 Program Memory Configuration (nX-4/300) 255 Words 1 - 10 nX-4/250/300 Core Instruction Manual Chapter 1 Architecture Address 0000H is the instruction execution start address when the system is reset. Allocated in 0001H through 00FFH are interrupt process routine start addresses when an interrupt occurs. See the user's manual for your device because the allocation is different depending on the type of device. ROM table data is transfered to data memory by a ROM table reference instruction. Melody data defines musical scale, tone length, and end tone used in a melody circuit. Melody data is automatically transfered to a melody circuit after its start address is indicated by a MSA instruction. Ths MSA instruction cannot be used for a device in which a melody circuit is not included. In the program memory space, 1 page consists of 4K words. The nX-4/250 core and nX-300 core has 16 pages. The LJMP and LCAL instructions can access the entire program memory space, but the JMP and CAL instructions can access only a page internal. The RA register indirect addressing instruction, PC relative addressing instruction, and PC based addressing instruction can access each page irrespective of the boundaries of pages 1 - 11 nX-4/250/300 Core Instruction Manual Chapter 1 Architecture 0FFFFH 0F000H 0EFFFH 0E000H 0DFFFH 0D000H 0CFFFH 0C000H 0BFFFH 0B000H 0AFFFH 0A000H 9FFFH 9000H 8FFFH 8000H 7FFFH 7000H 6FFFH 6000H 5FFFH 5000H 4FFFH 4000H 3FFFH 3000H 2FFFH 2000H 1FFFH 1000H 0FFFH 0000H Page 15 Page 14 Page 13 Page 12 Page 11 Page 10 Page 9 Page 8 Page 7 Page 6 Page 5 Page 4 Page 3 Page 2 Page 1 Page 0 JMP, CAL Space (4096 Words) LJMP, LCAL Space (65356 Words) Fig. 1-16 Pages in Program Memory Space (nX-4/300) 1 - 12 nX-4/250/300 Core Instruction Manual Chapter 1 Architecture 2.2.2 Data memory space Data memory space holds the data RAM and special function register (SFR). As indicated in Fig. 1-17 below, the data memory consists of 16 banks, with each bank unit having 256 nibbles in size. BANK0 is assigned to SFR space, and bank1 to 15 (3480 nibbles) are assigned to data RAM. 0FFFH 0F00H 0EFFH 0E00H 0DFFH 0D00H 0CFFH 0C00H 0BFFH BANK11 0B00H 0AFFH BANK10 0A00H 9FFH BANK9 900H 8FFH 800H 7FFH BANK7 700H 6FFH BANK6 600H 5FFH 500H 4FFH BANK4 400H 3FFH 300H 2FFH BANK2 200H 1FFH BANK1 100H 0FFH 000H 4 bits BANK0 SFR space (256 nibbles) 000H 4 bits Other SFR space BANK3 BANK5 BANK8 Data RAM space (3840 nibbles) 0FFH 0FEH 0FDH 0FCH 0FBH 0FAH 0F9H 0F8H 0F7H 0F6H 0F5H 0F4H 0F3H 0F2H 0F1H BANK15 BANK14 BANK13 BANK12 MIEF EBR CBR H L X Y SPH SP or SPL RSP RA3 RA2 RA1 RA0 Fig. 1-17 Data Memory Space Configuration 1 - 13 nX-4/250/300 Core Instruction Manual Chapter 1 Architecture 2.2.2.1 SFR space The 256-nibble SFR space from 000H to 0FFH contains the special function register (SFR) used to control peripheral functions connected to the CPU core. The 0F2H to 0FFH are allocated to CPU core registers as indicated in Table 1-2 below. Table 1-2 Register SFR Allocation Address 0F2H 0F3H 0F4H 0F5H 0F6H 0F7H 0F8H 0F9H 0FAH 0FBH 0FCH 0FDH 0FEH 0FFH (Note) RA0 register RA1 register RA2 register RA3 register Register stack pointer Stack pointer L Stack pointer H Y register X register L register H register Current bank register Extra bank register Master interrupt enable flag Register name symbol RA0 RA1 RA2 RA3 RSP SPL SPH Y X L H CBR EBR MIEF Content b3 a3 a7 a11 a15 rsp3 SP3 --* y3 x3 l3 h3 c3 e3 --* b2 a2 a6 a10 a14 rsp2 SP2 --* y2 x2 l2 h2 c2 e2 --* b1 a1 a5 a9 a13 rsp1 SP1 --* y1 x1 l1 h1 c1 e1 --* b0 a0 a4 a8 a12 rsp0 SP0 SP4 y0 x0 l0 h0 c0 e0 MIE R/W R/W R/W R/W R/W R/W R R R/W R/W R/W R/W R/W R/W R * = reserved bit : Always reads "1". Write is disabled. "R" indicates read-only and "R/W" indicates read and write are enabled. 1 - 14 nX-4/250/300 Core Instruction Manual Chapter 1 Architecture 2.2.3 External memory space The external memory space has an 8-bit data length data space, allocated from address 00000H to address 0FFFFH. The external memory space is configured as indicated in Fig. 1-18. 0FFFFH Data 65536 Bytes 0000H 8 Bits Fig. 1-18 External Memory Space Configuration 1 - 15 nX-4/250/300 Core Instruction Manual Chapter 1 Architecture 2.3 Addressing modes Addressing modes are classified as indicated in Table 1-3. Table 1-3 Addressing Mode Classification Classification Content Register direct Bit direct Immediate Register addressing modes Data memory addressing modes Direct SFR bank internal direct Current bank internal direct HL register indirect XY register indirect Extra bank HL register indirect Extra bank XY register indirect Post-incremented HL register indirect Post-incremented XY register indirect Post-incremented extra bank HL register indirect Post-incremented extra bank XY register indirect Bit direct Bit indirect Program memory addressing modes 64 K word direct 4K word page internal direct RA register indirect PC relative PC based External memory addressing modes RA register indirect Direct 2.3.1 Register addressing mode 2.3.1.1 Register direct addressing mode Instructions can be used to directly set the accumulator (A), HL register, XY register, RA3 to RA0 registers, current flag register (CFR), extra bank register (EBR) and flag register (FLAG). n Operand description * A, H, L, X, Y, CBR, EBR, FLAG * HL, XY, RA n Description example INCB HL ; Increment HL register 1 - 16 nX-4/250/300 Core Instruction Manual Chapter 1 Architecture 2.3.1.2 Bit direct addressing mode Instructions can be used to perform bit operations on the zero flag (Z), carry flag (C) and G flag of the flag register (FLAG). n Operand description * Z, C, G n Description example FCLR C ; Clear carry flag 2.3.1.3 Immediate addressing mode The numerical values in an instruction are directly treated as data. n Operand description * #i n Description example MOV CBR, #4H ; Write immediate data 4H to CBR 1 - 17 nX-4/250/300 Core Instruction Manual Chapter 1 Architecture 2.3.2 Data memory addressing modes The following data memory addressing modes are supported: Data memory addressing Direct addressing Direct addressing SFR bank internal direct addressing Current bank internal direct addressing Register indirect addressing HL register indirect addressing XY register indirect addressing Extra bank HL register indirect addressing Extra bank XY register indirect addressing Post-incremented HL register indirect addressing Post-incremented XY register indirect addressing Post-incremented extra bank HL register indirect addressing Post-incremented extra bank XY register indirect addressing The post-incremented indirect addressing mode can add +1 or +2 to the HL or XY register after instruction execution. * For +1 In the 4-bit unit operation mode, the HL register or XY register is incremented by one after instruction execution. If the HL or XY register overflows as a result (HL = 0 or XY = 0), the G flag is set to "1" . If there is no overflow, the G flag is cleared to "0". * For +2 In the 8-bit unit operation mode (ROM table reference instruction, external memory transfer instruction), the HL register or XY register is incremented by two after instruction execution. If the HL or XY register overflows as a result (HL > 0FFH or XY > 0FFH), the G flag is set to "1". If there is no overflow, the G flag is cleared to "0". [Note] The post-incremented indirect addressing mode should not be used for XY, HL, CBR, and EBR registers located in 0F9H to 0FEH of the SFR space. 1 - 18 nX-4/250/300 Core Instruction Manual Chapter 1 Architecture 2.3.2.1 Direct addressing mode The data memory space address is directly specified by the 12-bit address data in the instruction code. Address data a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 11 Data memory space address a11 10 a10 9 a9 8 a8 7 a7 6 a6 5 a5 4 a4 3 a3 2 a2 1 a1 0 a0 n Operand description * direct n Description example MOV 326H, A ; Transfers accumulator content to address 26H of bank 3 2.3.2.2 SFR bank internal direct addressing mode The data memory space SFR space (bank 0) is directly specified by the 8-bit address data in the instruction code. Address data a7 a6 a5 a4 a3 a2 a1 a0 11 Data memory space address 0 10 0 9 0 8 0 7 a7 6 a6 5 a5 4 a4 3 a3 2 a2 1 a1 0 a0 n Operand description * sfr n Description example MOV 36H, #0CH ; Write immediate data 0CH to address 36H of the SFR (bank0) 1 - 19 nX-4/250/300 Core Instruction Manual Chapter 1 Architecture 2.3.2.3 Current bank internal direct addressing mode The data memory space address is directly specified by the 8-bit address data in the current bank register (CBR). CBR c3 c2 c1 c0 a7 a6 a5 Address data a4 a3 a2 a1 a0 11 Data memory space address c3 10 c2 9 c1 8 c0 7 a7 6 a6 5 a5 4 a4 3 a3 2 a2 1 a1 0 a0 n Operand description * cur n Description example INC 32H ; Increments the content of address 32H in the bank indicated by CBR, and stores the result to address 32H and accumulator 2.3.2.4 HL register indirect addressing mode The data memory space address is indirectly specified by the current bank register (CBR) and the HL register. CBR c3 c2 c1 c0 h3 h2 H h1 h0 l3 l2 L l1 l0 11 Data memory space address c3 10 c2 9 c1 8 c0 7 h3 6 h2 5 h1 4 h0 3 l3 2 l2 1 l1 0 l0 n Operand description * [HL] or C:[HL] n Description example MOV [HL], A ; The accumulator content is transferred to the data memory specified by the CBR and HL registers 1 - 20 nX-4/250/300 Core Instruction Manual Chapter 1 Architecture 2.3.2.5 XY register indirect addressing mode The data memory space address is indirectly specified by the current bank register (CBR) and the XY register. CBR c3 c2 c1 c0 x3 x2 X x1 x0 y3 y2 Y y1 y0 11 Data memory space address c3 10 c2 9 c1 8 c0 7 x3 6 x2 5 x1 4 x0 3 y3 2 y2 1 y1 0 y0 n Operand description * [XY] or C:[XY] n Description example DEC [XY] ; The data memory content specified by the CBR and XY registers is decremented, and the result stored to the data memory and accumulator. 2.3.2.6 Extra bank HL indirect addressing mode The data memory space address is indirectly specified by the extra bank register (EBR) and the HL register. EBR e3 e2 e1 e0 h3 h2 H h1 h0 l3 l2 L l1 l0 11 Data memory space address e3 10 e2 9 e1 8 e0 7 h3 6 h2 5 h1 4 h0 3 l3 2 l2 1 l1 0 l0 n Operand description * E:[HL] n Description example ROR E:[HL] ; The data memory content specified by the EBR and HL registers is rotated right, including the carry, and the result stored to the data memory and accumulator. 1 - 21 nX-4/250/300 Core Instruction Manual Chapter 1 Architecture 2.3.2.7 Extra bank XY indirect addressing mode The data memory space address is indirectly specified by the extra bank register (EBR) and the XY register. EBR e3 e2 e1 e0 x3 x2 X x1 x0 y3 y2 Y y1 y0 11 Data memory space address e3 10 e2 9 e1 8 e0 7 x3 6 x2 5 x1 4 x0 3 y3 2 y2 1 y1 0 y0 n Operand description * E:[XY] n Description example AND E:[XY], A ; The logical product of the data memory content specified by the EBR and XY registers and the accumulator is stored to the data memory and accumulator. 2.3.2.8 HL register indirect addressing mode with post-increment The data memory space address is indirectly specified by the current bank register (CBR) and the HL register. After execution the HL register is incremented by +1 or +2. CBR c3 c2 c1 c0 h3 h2 H h1 h0 l3 l2 L l1 l0 11 Data memory space address c3 10 c2 9 c1 8 c0 7 h3 6 h2 5 h1 4 h0 3 l3 2 l2 1 l1 0 l0 n Operand description * [HL+] or C:[HL+] n Description example MOV [HL+], A ; The accumulator content is transferred to the data memory specified by the CBR and HL registers and then the HL register is incremented by one. 1 - 22 nX-4/250/300 Core Instruction Manual Chapter 1 Architecture 2.3.2.9 XY register indirect addressing mode with post-increment The data memory space address is indirectly specified by the current bank register (CBR) and the XY register. After execution the XY register is incremented by +1 or +2. CBR c3 c2 c1 c0 x3 x2 X x1 x0 y3 y2 Y y1 y0 11 Data memory space address c3 10 c2 9 c1 8 c0 7 x3 6 x2 5 x1 4 x0 3 y3 2 y2 1 y1 0 y0 n Operand description * [XY+] or C:[XY+] n Description example XOR [XY+], A ; The results of an exlusive-OR between accumulator and the data memory content specified by the CBR and XY registers are stored to the accumulator and data memory. Then the XY register is incremented by one. 2.3.2.10 Extra bank HL register indirect addressing mode with post-increment The data memory space address is indirectly specified by the extra bank register (EBR) and the HL register. After execution the HL register is incremented by +1 or +2. EBR e3 e2 e1 e0 h3 h2 H h1 h0 l3 l2 L l1 l0 11 Data memory space address e3 10 e2 9 e1 8 e0 7 h3 6 h2 5 h1 4 h0 3 l3 2 l2 1 l1 0 l0 n Operand description * E:[HL+] n Description example MOV E:[HL+], #00H ; Immediate data 00H is transferred to the accumulator and the data memory specified by the EBR and HL registers, then the HL register is incremented by one. 1 - 23 nX-4/250/300 Core Instruction Manual Chapter 1 Architecture 2.3.2.11 Extra bank XY register indirect addressing mode with post-increment The data memory space address is indirectly specified by the extra bank register (EBR) and the XY register. After execution the XY register is incremented by +1 or +2. EBR e3 e2 e1 e0 x3 x2 X x1 x0 y3 y2 Y y1 y0 11 Data memory space address e3 10 e2 9 e1 8 e0 7 x3 6 x2 5 x1 4 x0 3 y3 2 y2 1 y1 0 y0 n Operand description * E:[XY+] n Description example MOV E:[XY+], A ; The accumulator content is transferred to the data memory specified by the EBR and XY registers, then the XY register is incremented by one. 2.3.2.12 Bit direct addressing mode Executes data memory bit operations, which may be bit operations in 1-bit units (specified with ".n") or multi-bit operations (specified with "#m"). n Operand description * [HL].n, [XY].n, C:[HL].n, C:[XY].n, E:[HL].n, E:[XY].n, [HL+].n, [XY+].n, E:[HL+].n, E:[XY+].n, cur.n (n = 0 ~ 3, 0:LSB, 3:MSB) n Description example BCLR [XY].3 ; The third bit of the data memory specified by the CBR and XY register is cleared, and the result stored to the data memory and accumulator. n Operand description * #m n Description example MCLR [XY].#3H ; Bits 0 and 1 of the data memory specified by the CBR and XY register are cleared, and the result stored to the data memory and accumulator. 1 - 24 nX-4/250/300 Core Instruction Manual Chapter 1 Architecture 2.3.2.13 Bit indirect addressing mode Executes data memory bit operations. The operated bit is specified by the content of the accumulator (A). n Operand description * A n Description example MTST 35H, A ; When A=3H, bits 0,1 of address 35H of the SFR (bank 0) are tested, and if either or both is zero the Z flag is set. 1 - 25 nX-4/250/300 Core Instruction Manual Chapter 1 Architecture 2.3.3 Addressing modes for program memory 2.3.3.1 64K word direct addressing mode 16-bit address data are used to address the entire program memory space. n Operand description * cadr16 n Description example MOVLB [HL], 0FFEH ; The lower 8bits of program memory address 0FFEH are transferred to the data memory specified by CBR and HL registers, and to the next address in data memory. Program memory 3FFFH or 0FFFFH Data memory CBR CBR 15 0FFEH 12 11 87 43 0 + + H H L L +1 n Description example LJMP 0234H ; Branch to the program memory address specified by the 16-bit direct address 1 - 26 nX-4/250/300 Core Instruction Manual Chapter 1 Architecture 2.3.3.2 4K word page addressing mode 12-bit address data is used to address the program memory page. n Operand description * cadr12 n Description example JMP 123H ; Branch to the program memory address within that page, specified by the 12-bit address 2.3.3.3 RA register indirect addressing mode The program memory space address is indirectly specified with the 16-bit address data in the RA register. RA3 RA register RA2 a9 a8 a7 RA1 a6 a5 a4 a3 RA0 a2 a1 a0 a15 a14 a13 a12 a11 a10 15 Program memory space address 14 13 12 11 10 9 a9 8 a8 7 a7 6 a6 5 a5 4 a4 3 a3 2 a2 1 a1 0 a0 a15 a14 a13 a12 a11 a10 n Operand description * [RA] n Description example MOVLB [XY], [RA] ; The lower 8 bits of program memory address specified by RA are transferred to the data memory specified by CBR and XY registers, and to the next address in data memory 1 - 27 nX-4/250/300 Core Instruction Manual Chapter 1 Architecture Program memory 3FFFH Data memory CBR + 15 12 11 RA3 RA2 RA1 RA0 87 43 0 CBR + X X Y Y +1 0000H [Note] The RA registers from 0F2F to 0F5H of SFR space and XY, HL, CBR and EBR registers from 0F9H to 0FEH should not be addressed as a transfer destination to data memory. If they are addressed, the contents of the addressed registers are undefined. 2.3.3.4 PC relative addressing mode The 8-bit address data in the instruction code is expanded to 16 bits, and the program branches to the address equal to that plus the address (PC value) for the next instruction. As a result, this type of addressing can specify a range of bytes from -128 to +127, centered on the next instruction. n Operand description * radr8 n Description example SJMP 35H ; Jumps to the address equal to the address for the next instuction plus 35H. 1 - 28 nX-4/250/300 Core Instruction Manual Chapter 1 Architecture 2.3.3.5 PC based addressing mode The current address (PC value) is added to the content of the accumulator, and the program branches to that address plus one. Depending on the content of the accumulator, this gives 16 possible results. n Operand description * PC + A n Description example JMP PC+A ; Jumps to the address equal to the address for the next instruction (PC + 1) plus the accumulator content. 2.3.4 Addressing mode for external memory 2.3.4.1 RA register indirect addressing mode The external memory space address is indirectly specified by the 16-bit address data of the RA register. RA3 RA register RA2 a9 a8 a7 RA1 a6 a5 a4 a3 RA0 a2 a1 a0 a15 a14 a13 a12 a11 a10 15 External memory space address 14 13 12 11 10 9 a9 8 a8 7 a7 6 a6 5 a5 4 a4 3 a3 2 a2 1 a1 0 a0 a15 a14 a13 a12 a11 a10 n Operand description * [RA] n Description example MOVXB [HL], [RA] ; The content of the external memory specified by RA is transferred to the data memory specified by CBR and HL registers, and to the next address in data memory. [Note] The RA registers from 0F2F to 0F5H of SFR space and XY, HL, CBR, EBR registers from 0F9H to 0FEH should not be addressed as a transfer destination to data memory. If they are addressed, the contents of the addressed registers are undefined. 1 - 29 nX-4/250/300 Core Instruction Manual Chapter 1 Architecture External memory 0FFFFH Data memory CBR + 7 RA3 RA2 RA1 RA0 43 0 CBR + H H L L +1 0000H 2.3.4.2 Direct addressing mode The 16-bit address data is used to address all external memory space. n Operand description * xadr16 n Description example MOVXB [HL], 0FDCH; The content of external memory address 0FDCH is transferred to the data memory specified by CBR and HL registers, and to the next address in data memory. External memory 0FFFFH Data memory CBR + 7 0FDCH 43 0 CBR + H H L L +1 0000H [Note] The RA registers from 0F2F to 0F5H of SFR space and XY, HL, CBR and EBR registers from 0F9H to 0FEH should not be addressed as a transfer destination to data memory. If they are addressed, the contents of the addressed registers are undefined. 1 - 30 Chapter 2 INSTRUCTION SET This chapter presents details on the function of the nX-4/250 core and nX-4/300 core instructions. nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set 1. OVERVIEW The nX-4/250 core and nX-4/300 core instruction codes are 16-bit length, and most instructions operate at one word per cycle. The nX/-4/250 core and nX/300 core have 440 kinds of instruction, and 450 kinds of instruction respectively. nX-4/250 nX-4/300 * Transfer instructions .............................................................. 38 types 38 types * Rotate instructions ................................................................. 20 types 20 types * Increment/decrement instructions ......................................... 20 types 20 types * Arithmetic operation instructions ........................................... 96 types 96 types * Comparison instructions ........................................................ 19 types 19 types * Logical operation instructions ............................................... 57 types 57 types * Mask operation instructions .................................................. 46 types 50 types * Bit operation instructions ....................................................... 36 types 40 types * ROM table reference instructions .......................................... 32 types 32 types * External memory transfer instructions ................................... 32 types 32 types * Stack operation instructions .................................................. 4 types 4 types * Flag operation instructions .................................................... 6 types 8 types * Branch instructions ................................................................ 4 types 4 types * Conditional branch instructions ............................................. 7 types 7 types * Call/return instructions ........................................................... 5 types 5 types * Control instructions ............................................................... 18 types 18 types These instructions can be classified by word length and machine cycle as shown below. * 1 word/1 machine cycle ......................................................... 369 types 379 types * 1 word/2 machine cycles ....................................................... 28 types 28 types * 1 word/3 machine cycles ....................................................... 8 types 8 types * 2 words/2 machine cycles ..................................................... 2 types 2 types * 2 words/3 machine cycles ..................................................... 33 types 33 types Instructions have the following functions: (1) Transfer instructions These instructions handle data memory transfer and immediate data transfer between accumulator and data memory. Rotate instructions These instructions rotate data memory left and right. Increment/decrement instructions These instructions handle data memory increment and decrement. Arithmetic operation instructions These instructions handle add and subtract operations for data memory and accumulator, or data memory and immediate data. Comparison instructions These instructions handle comparison between data memory and accumulator, or data memory and immediate data. Logical operation instructions These instructions handle logical product, logical add and exclusive OR between data (2) (3) (4) (5) (6) 2-1 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set (7) memory and accumulator, or data memory and immediate data. Mask operation instructions These instructions handle set, clear and transfer operations for non-masked data memory bits. Bit operation instructions These instructions handle set, clear and transfer operations for special data memory bits. ROM table reference instructions These instructions handle transfer of program memory table data to data memory. (8) (9) (10) External memory transfer instructions These instructions handle transfer of external memory data to data memory. (11) Stack operation instructions These instructions handle save of flag register, accumulator, HL registers, XY register, extra bank register and current bank register to the register stack, and restore operations. (12) Flag operation instructions These instructions handle set and clear operations for the zero flag, carry flag and G flag. (13) Branch instructions These instructions execute branches to program memory absolute and relative addresses. (14) Conditional branch instructions These instructions execute branches as per the contents of the zero flag, carry flag and G flag. (15) Call/return instructions These instructions execute subroutine call/return processing, and return from interrupt routines. (16) Control instructions These instructions set the current bank register, extra bank register, RA0 to RA3 registers, HL register, and XY register, as well as starting melody and halting the CPU. 2-2 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set 2. OPERAND EXPRESSION There are two types of instructions: those which have one or two operands, and those which have none. Operands are specified in the order of 2-3 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set [Addressing names] * direct ............................. Direct addressing * sfr .................................. SFR bank (bank 0) internal direct addressing * cur ................................. Current bank internal direct addressing * bank:[reg] ...................... Cumulative name for register indirect addressing * [HL] ................................ HL register indirect addressing * [XY] ................................ XY register indirect addressing * C:[HL] ............................ HL register indirect addressing * C:[XY] ............................ XY register indirect addressing * E:[HL] ............................. Extra bank HL register indirect addressing * E:[XY] ............................. Extra bank XY register indirect addressing * bank:[reg+] .................... Cumulative name for post-incremented register indirect addressing * [HL+] .............................. Post-incremented HL register indirect addressing * [XY+] .............................. Post-incremented XY register indirect addressing * C:[HL+] .......................... Post-incremented HL register indirect addressing * C:[XY+] .......................... Post-incremented XY register indirect addressing * E:[HL+] .......................... Post-incremented extra bank HL register indirect addressing * E:[XY+] ........................... Post-incremented extra bank XY register indirect addressing * [RA] ................................ RA register indirect addressing * cadr16 ........................... 64K word internal direct addressing * cadr12 ........................... 4K word page internal addressing * radr8 .............................. PC relative addressing * PC+A ............................. PC based addressing [Other] * ....................................... Indicates data replacement direction * ...................................... Data swap * + .................................... Add * - ..................................... Subtract * = .................................... Equal * ........................................ Not equal * ^ .................................... Logical product * ........................................ Logical add * " ........................................ Exclusive logical add * -- ................................... Inverse (complement of 1) 2-4 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set 3. LIST OF INSTRUCTIONS The format used in the list of instructions is indicated below. INSTRUCTION CODE FLAG MNEMONIC OPERATION WC 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Z C G PAGE Refer to this page for additional information. Flags marked with a circle are affected by instruction execution, and those that are not affected with a dash. Indicates the instruction code content. For a 2-word long instruction, the first part shows the first word, and the second part the second word. Indicates the number of machine cycles needed to execute the instruction. Indicates the instruction word length. Indicates the instruction function. Indicates the short-from name for the instruction. [Note] Only the nX-4/300 core has MMOV, BMOV, FCLR FLAG and FSET FLAG instructions. 2-5 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set l Transfer Instructions INSTRUCTION CODE MNEMONIC MOV direct,A MOV [HL],A MOV [XY],A MOV E:[HL],A MOV E:[XY],A MOV [HL+],A MOV [XY+],A OPERATION directA [HL]A [XY]A E:[HL]A E:[XY]A [HL]A,HLHL+1 [XY]A,XYXY+1 WC FLAG 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Z C G PAGE 1 1 1 1 0 0 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 -- -- -- 1 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 ------ 1 1 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 ------ 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 ------ 1 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 -- -- -- 66 1 1 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 0 ----m 1 1 0 0 0 0 0 1 0 0 0 0 1 1 1 0 0 0 ----m 1 1 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 ----m 1 1 0 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 ----m 1 1 0 1 0 0 i3 i2 i1 i0 r7 r6 r5 r4 r3 r2 r1 r0 m -- -- 1 1 0 0 0 0 0 1 1 0 0 1 1 0 i3 i2 i1 i0 m -- -- 1 1 0 0 0 0 0 1 1 0 0 1 1 1 i3 i2 i1 i0 m -- -- 1 1 0 0 0 0 0 1 1 0 0 1 0 0 i3 i2 i1 i0 m -- -- 1 1 0 0 0 0 0 1 1 0 0 1 0 1 i3 i2 i1 i0 m -- -- 67 MOV E:[HL+],A E:[HL]A,HLHL+1 MOV E:[XY+],A E:[XY]A,XYXY+1 MOV cur,#i4 MOV [HL],#i4 MOV [XY],#i4 cur,Ai4 [HL],Ai4 [XY],Ai4 MOV E:[HL],#i4 E:[HL],Ai4 MOV E:[XY],#i4 E:[XY],Ai4 MOV [HL+],#i4 [HL],Ai4,HLHL+1 1 1 0 0 0 0 0 1 1 1 0 1 1 0 i3 i2 i1 i0 m -- m MOV [XY+],#i4 [XY],Ai4,XYXY+1 1 1 0 0 0 0 0 1 1 1 0 1 1 1 i3 i2 i1 i0 m -- m MOV E:[HL+],#i4 E:[HL],Ai4,HLHL+1 1 1 0 0 0 0 0 1 1 1 0 1 0 0 i3 i2 i1 i0 m -- m MOV E:[XY+],#i4 E:[XY],Ai4,XYXY+1 1 1 0 0 0 0 0 1 1 1 0 1 0 1 i3 i2 i1 i0 m -- m MOV A,#i4 MOV A,direct MOV A,[HL] MOV A,[XY] MOV A,E:[HL] MOV A,E:[XY] MOV A,[HL+] MOV A,[XY+] Ai4 Adirect A[HL] A[XY] AE:[HL] AE:[XY] A[HL],HLHL+1 A[XY],XYXY+1 1 1 0 0 0 0 0 0 0 1 1 1 0 0 i3 i2 i1 i0 m -- -- 65 1 1 1 1 0 1 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 m -- -- 1 1 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 m---- 1 1 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 m---- 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 m---- 1 1 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 m -- -- 64 1 1 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 0 m--m 1 1 0 0 0 0 0 0 1 1 0 0 1 1 1 0 0 0 m--m 1 1 0 0 0 0 0 0 1 1 0 0 0 0 1 0 0 0 m--m 1 1 0 0 0 0 0 0 1 1 0 0 0 1 1 0 0 0 m--m MOV A,E:[HL+] AE:[HL],HLHL+1 MOV A,E:[XY+] AE:[XY],XYXY+1 2-6 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set INSTRUCTION CODE MNEMONIC XCH A,sfr XCH A,cur XCH A,[HL] XCH A,[XY] XCH A,E:[HL] XCH A,E:[XY] XCH A,[HL+] XCH A,[XY+] XCH A,E:[HL+] XCH A,E:[XY+] OPERATION Asfr Acur A[HL] A[XY] AE:[HL] AE:[XY] A[HL],HLHL+1 A[XY],XYXY+1 WC FLAG 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Z C G 1 1 0 0 1 0 1 1 1 0 r7 r6 r5 r4 r3 r2 r1 r0 -- -- -- 1 1 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 1 ------ 1 1 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 1 ------ 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 ------ 1 1 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 1 ------ PAGE 1 1 0 0 1 1 1 1 1 0 r7 r6 r5 r4 r3 r2 r1 r0 -- -- -- 97 1 1 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 ----m 1 1 0 0 0 0 0 0 1 1 0 0 1 1 1 0 0 1 ----m AE:[HL],HLHL+1 1 1 0 0 0 0 0 0 1 1 0 0 0 0 1 0 0 1 -- -- m AE:[XY],XYXY+1 1 1 0 0 0 0 0 0 1 1 0 0 0 1 1 0 0 1 -- -- m 2-7 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set l Rotate Instructions INSTRUCTION CODE MNEMONIC ROL sfr ROL cur ROL [HL] ROL [XY] ROL E:[HL] ROL E:[XY] ROL [HL+] ROL [XY+] ROL E:[HL+] ROL E:[XY+] ROR sfr ROR cur ROR [HL] ROR [XY] ROR E:[HL] ROR E:[XY] ROR [HL+] ROR [XY+] ROR E:[HL+] ROR E:[XY+] OPERATION C{3sfr0}C,Asfr C{3[HL]0}C,A[HL] C{3[XY]0}C,A[XY] WC FLAG PAGE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Z C G 1 1 0 0 1 0 0 0 1 0 r7 r6 r5 r4 r3 r2 r1 r0 m m -- 1 1 0 0 0 0 0 1 0 0 0 0 1 0 0 1 1 0 mm-- 1 1 0 0 0 0 0 1 0 0 0 0 1 1 0 1 1 0 mm-- C{3cur0}C,Acur 1 1 0 0 1 1 0 0 1 0 r7 r6 r5 r4 r3 r2 r1 r0 m m -- C{3E:[HL]0}C,AE:[HL] 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 0 m m -- C{3E:[XY]0}C,AE:[XY] 1 1 0 0 0 0 0 1 0 0 0 0 0 1 0 1 1 0 m m -- C{3[HL]0}C,A[HL], 1 1 0 0 0 0 0 1 0 0 0 0 1 0 1 1 1 0 mmm HLHL+1 C{3[XY]0}C,A[XY], 1 1 0 0 0 0 0 1 0 0 0 0 1 1 1 1 1 0 mmm XYXY+1 C{3E:[HL]0}C, AE:[HL],HLHL+1 C{3E:[XY]0}C, AE:[XY],XYXY+1 CAE{3sfr0}AEC,Asfr 1 1 0 0 0 0 0 1 0 0 0 0 0 0 1 1 1 0 mmm 1 1 0 0 0 0 0 1 0 0 0 0 0 1 1 1 1 0 mmm 1 1 0 0 1 0 0 0 1 1 r7 r6 r5 r4 r3 r2 r1 r0 m m -- 87 CAE{3cur0}AEC,Acur 1 1 0 0 1 1 0 0 1 1 r7 r6 r5 r4 r3 r2 r1 r0 m m -- CAE{3[HL]0}AEC,A[HL] 1 1 0 0 0 0 0 1 0 0 0 0 1 0 0 1 1 1 m m -- CAE{3[XY]0}AEC,A[XY] 1 1 0 0 0 0 0 1 0 0 0 0 1 1 0 1 1 1 m m -- CAE{3E:[HL]0}AEC,AE:[HL] 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 1 m m -- CAE{3E:[XY]0}AEC,AE:[XY] 1 1 0 0 0 0 0 1 0 0 0 0 0 1 0 1 1 1 m m -- CAE{3[HL]0}AEC,A[HL], 1 1 0 0 0 0 0 1 0 0 0 0 1 0 1 1 1 1 mmm HLHL+1 CAE{3[XY]0}AEC,A[XY], 1 1 0 0 0 0 0 1 0 0 0 0 1 1 1 1 1 1 mmm XYXY+1 CAE{3E:[HL]0}AEC, AE:[HL],HLHL+1 CAE{3E:[XY]0}AEC, AE:[XY],XYXY+1 1 1 0 0 0 0 0 1 0 0 0 0 0 0 1 1 1 1 mmm 1 1 0 0 0 0 0 1 0 0 0 0 0 1 1 1 1 1 mmm 88 2-8 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set l Increment/decrement Instructions INSTRUCTION CODE MNEMONIC INC sfr INC cur INC [HL] INC [XY] INC E:[HL] INC E:[XY] INC [HL+] INC [XY+] INC E:[HL+] INC E:[XY+] DEC sfr DEC cur DEC [HL] DEC [XY] DEC E:[HL] DEC E:[XY] DEC [HL+] DEC [XY+] DEC E:[HL+] DEC E:[XY+] OPERATION sfr,Asfr+1 cur,Acur+1 [HL],A[HL]+1 [XY],A[XY]+1 WC FLAG PAGE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Z C G 1 1 0 0 1 0 0 0 0 0 r7 r6 r5 r4 r3 r2 r1 r0 m m -- 1 1 0 0 1 1 0 0 0 0 r7 r6 r5 r4 r3 r2 r1 r0 m m -- 1 1 0 0 0 0 0 1 0 1 0 0 1 0 0 0 0 0 mm-- 1 1 0 0 0 0 0 1 0 1 0 0 1 1 0 0 0 0 mm-- E:[HL],AE:[HL]+1 1 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 m m -- E:[XY],AE:[XY]+1 1 1 0 0 0 0 0 1 0 1 0 0 0 1 0 0 0 0 m m -- [HL],A[HL]+1, HLHL+1 [XY],A[XY]+1, XYXY+1 1 1 0 0 0 0 0 1 0 1 0 0 1 0 1 0 0 0 mmm 1 1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 0 mmm 57 E:[HL],AE:[HL]+1, 1 1 0 0 0 0 0 1 0 1 0 0 0 0 1 0 0 0 mmm HLHL+1 E:[XY],AE:[XY]+1, 1 1 0 0 0 0 0 1 0 1 0 0 0 1 1 0 0 0 mmm XYXY+1 sfr,Asfr-1 cur,Acur-1 [HL],A[HL]-1 [XY],A[XY]-1 1 1 0 0 1 0 0 0 0 1 r7 r6 r5 r4 r3 r2 r1 r0 m m -- 1 1 0 0 1 1 0 0 0 1 r7 r6 r5 r4 r3 r2 r1 r0 m m -- 1 1 0 0 0 0 0 1 0 1 0 0 1 0 0 0 0 1 mm-- 1 1 0 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 mm-- E:[HL],AE:[HL]-1 1 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 m m -- E:[XY],AE:[XY]-1 1 1 0 0 0 0 0 1 0 1 0 0 0 1 0 0 0 1 m m -- [HL],A[HL]-1, HLHL+1 [XY],A[XY]-1, XYXY+1 1 1 0 0 0 0 0 1 0 1 0 0 1 0 1 0 0 1 mmm 1 1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 mmm 50 E:[HL],AE:[HL]-1, 1 1 0 0 0 0 0 1 0 1 0 0 0 0 1 0 0 1 mmm HLHL+1 E:[XY],AE:[XY]-1, 1 1 0 0 0 0 0 1 0 1 0 0 0 1 1 0 0 1 mmm XYXY+1 2-9 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set l Arithmetic Operation Instructions INSTRUCTION CODE MNEMONIC ADD sfr,A ADD cur,A ADD [HL],A ADD [XY],A ADD E:[HL],A ADD E:[XY],A ADD [HL+],A ADD [XY+],A ADD E:[HL+],A ADD E:[XY+],A ADD cur,#i4 ADD [HL],#i4 ADD [XY],#i4 OPERATION sfr,Asfr+A cur,Acur+A [HL],A[HL]+A [XY],A[XY]+A WC FLAG PAGE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Z C G 1 1 0 0 1 0 0 1 0 0 r7 r6 r5 r4 r3 r2 r1 r0 m m -- 1 1 0 0 1 1 0 1 0 0 r7 r6 r5 r4 r3 r2 r1 r0 m m -- 1 1 0 0 0 0 0 1 0 1 0 0 1 0 0 0 1 0 mm-- 1 1 0 0 0 0 0 1 0 1 0 0 1 1 0 0 1 0 mm-- E:[HL],AE:[HL]+A 1 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 1 0 m m -- E:[XY],AE:[XY]+A 1 1 0 0 0 0 0 1 0 1 0 0 0 1 0 0 1 0 m m -- [HL],A[HL]+A, HLHL+1 [XY],A[XY]+A, XYXY+1 37 1 1 0 0 0 0 0 1 0 1 0 0 1 0 1 0 1 0 mmm 1 1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 1 0 mmm E:[HL],AE:[HL]+A, 1 1 0 0 0 0 0 1 0 1 0 0 0 0 1 0 1 0 mmm HLHL+1 E:[XY],AE:[XY]+A, 1 1 0 0 0 0 0 1 0 1 0 0 0 1 1 0 1 0 mmm XYXY+1 cur,Acur+i4 [HL],A[HL]+i4 [XY],A[XY]+i4 1 1 1 0 0 0 i3 i2 i1 i0 r7 r6 r5 r4 r3 r2 r1 r0 m m -- 1 1 0 0 0 0 0 0 0 0 1 0 1 0 i3 i2 i1 i0 m m -- 1 1 0 0 0 0 0 0 0 0 1 0 1 1 i3 i2 i1 i0 m m -- ADD E:[HL],#i4 E:[HL],AE:[HL]+i4 1 1 0 0 0 0 0 0 0 0 1 0 0 0 i3 i2 i1 i0 m m -- ADD E:[XY],#i4 E:[XY],AE:[XY]+i4 1 1 0 0 0 0 0 0 0 0 1 0 0 1 i3 i2 i1 i0 m m -- ADD [HL+],#i4 ADD [XY+],#i4 ADD E:[HL+],#i4 ADD E:[XY+],#i4 ADC sfr,A ADC cur,A ADC [HL],A ADC [XY],A ADC E:[HL],A ADC E:[XY],A [HL],A[HL]+i4, HLHL+1 [XY],A[XY]+i4, XYXY+1 1 1 0 0 0 0 0 0 0 1 1 0 1 0 i3 i2 i1 i0 m m m 1 1 0 0 0 0 0 0 0 1 1 0 1 1 i3 i2 i1 i0 m m m 38 E:[HL],AE:[HL]+i4, 1 1 0 0 0 0 0 0 0 1 1 0 0 0 i3 i2 i1 i0 m m m HLHL+1 E:[XY],AE:[XY]+i4, 1 1 0 0 0 0 0 0 0 1 1 0 0 1 i3 i2 i1 i0 m m m XYXY+1 sfr,Asfr+A+C cur,Acur+A+C [HL],A[HL]+A+C [XY],A[XY]+A+C 1 1 0 0 1 0 0 1 0 1 r7 r6 r5 r4 r3 r2 r1 r0 m m -- 1 1 0 0 1 1 0 1 0 1 r7 r6 r5 r4 r3 r2 r1 r0 m m -- 1 1 0 0 0 0 0 1 0 1 0 0 1 0 0 0 1 1 mm-- 1 1 0 0 0 0 0 1 0 1 0 0 1 1 0 0 1 1 mm-- 34 E:[HL],AE:[HL]+A+C 1 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 1 1 m m -- E:[XY],AE:[XY]+A+C 1 1 0 0 0 0 0 1 0 1 0 0 0 1 0 0 1 1 m m -- 2 - 10 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set INSTRUCTION CODE MNEMONIC ADC [HL+],A ADC [XY+],A ADC E:[HL+],A ADC E:[XY+],A ADCD sfr,A ADCD cur,A ADCD [HL],A ADCD [XY],A ADCD E:[HL],A ADCD E:[XY],A OPERATION WC FLAG PAGE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Z C G [HL],A[HL]+A+C, 1 1 0 0 0 0 0 1 0 1 0 0 1 0 1 0 1 1 mmm HLHL+1 [XY],A[XY]+A+C, 1 1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 1 1 mmm XYXY+1 E:[HL],AE:[HL]+A+C, 1 1 0 0 0 0 0 1 0 1 0 0 0 0 1 0 1 1 mmm HLHL+1 E:[XY],AE:[XY]+A+C, 1 1 0 0 0 0 0 1 0 1 0 0 0 1 1 0 1 1 mmm XYXY+1 sfr,Adecimal adjustment {sfr+A+C} 1 1 0 0 1 0 0 1 1 0 r7 r6 r5 r4 r3 r2 r1 r0 m m -- 34 cur,Adecimal adjustment 1 1 0 0 1 1 0 1 1 0 r7 r6 r5 r4 r3 r2 r1 r0 m m -- {cur+A+C} [HL],Adecimal adjustment 1 1 0 0 0 0 0 1 0 1 0 0 1 0 0 1 0 0 mm-- {[HL]+A+C} [XY],Adecimal adjustment 1 1 0 0 0 0 0 1 0 1 0 0 1 1 0 1 0 0 mm-- {[XY]+A+C} E:[HL],Adecimal 1 1 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 0 mm-- adjustment {E:[HL]+A+C} E:[XY],Adecimal 1 1 0 0 0 0 0 1 0 1 0 0 0 1 0 1 0 0 mm-- adjustment {E:[XY]+A+C} [HL],Adecimal adjustment {[HL]+A+C}, HLHL+1 [XY],Adecimal adjustment {[XY]+A+C}, XYXY+1 1 1 0 0 0 0 0 1 0 1 0 0 1 0 1 1 0 0 mmm 35 ADCD [HL+],A ADCD [XY+],A 1 1 0 0 0 0 0 1 0 1 0 0 1 1 1 1 0 0 mmm E:[HL],Adecimal ADCD E:[HL+],A adjustment {E:[HL]+A+C}, 1 1 0 0 0 0 0 1 0 1 0 0 0 0 1 1 0 0 m m m HLHL+1 E:[XY],Adecimal ADCD E:[XY+],A adjustment {E:[XY]+A+C}, 1 1 0 0 0 0 0 1 0 1 0 0 0 1 1 1 0 0 m m m XYXY+1 2 - 11 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set INSTRUCTION CODE MNEMONIC ADCJ cur,n ADCJ [HL],n ADCJ [XY],n ADCJ E:[HL],n ADCJ E:[XY],n ADCJ [HL+],n ADCJ [XY+],n ADCJ E:[HL+],n ADCJ E:[XY+],n SUB sfr,A SUB cur,A SUB [HL],A SUB [XY],A SUB E:[HL],A SUB E:[XY],A SUB [HL+],A SUB [XY+],A SUB E:[HL+],A SUB E:[XY+],A OPERATION cur,Abase-n adjustment {cur+C} WC FLAG 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Z C G PAGE 1 1 0 0 0 1 0 n2 n1 n0 r7 r6 r5 r4 r3 r2 r1 r0 m m -- [HL],Abase-n adjustment 1 1 0 0 0 0 0 1 1 0 0 0 1 0 0 n2 n1 n0 m m -- {[HL]+C} [XY],Abase-n adjustment 1 1 0 0 0 0 0 1 1 0 0 0 1 1 0 n2 n1 n0 m m -- {[XY]+C} E:[HL],Abase-n adjustment 1 {E:[HL]+C} E:[XY],Abase-n adjustment 1 {E:[XY]+C} 1 0 0 0 0 0 1 1 0 0 0 0 0 0 n2 n1 n0 m m -- 1 0 0 0 0 0 1 1 0 0 0 0 1 0 n2 n1 n0 m m -- 36 [HL],Abase-n adjustment 1 1 0 0 0 0 0 1 1 1 0 0 1 0 0 n2 n1 n0 m m m {[HL]+C},HLHL+1 [XY],Abase-n adjustment 1 1 0 0 0 0 0 1 1 1 0 0 1 1 0 n2 n1 n0 m m m {[XY]+C},XYXY+1 E:[HL],Abase-n adjustment 1 1 0 0 0 0 0 1 1 1 0 0 0 0 0 n2 n1 n0 m m m {E:[HL]+C},HLHL+1 E:[XY],Abase-n adjustment 1 1 0 0 0 0 0 1 1 1 0 0 0 1 0 n2 n1 n0 m m m {E:[XY]+C},XYXY+1 sfr,Asfr-A cur,Acur-A [HL],A[HL]-A [XY],A[XY]-A 1 1 0 0 1 0 0 1 1 1 r7 r6 r5 r4 r3 r2 r1 r0 m m -- 1 1 0 0 1 1 0 1 1 1 r7 r6 r5 r4 r3 r2 r1 r0 m m -- 1 1 0 0 0 0 0 1 0 1 0 0 1 0 0 1 0 1 mm-- 1 1 0 0 0 0 0 1 0 1 0 0 1 1 0 1 0 1 mm-- E:[HL],AE:[HL]-A 1 1 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 m m -- E:[XY],AE:[XY]-A 1 1 0 0 0 0 0 1 0 1 0 0 0 1 0 1 0 1 m m -- [HL],A[HL]-A, HLHL+1 [XY],A[XY]-A, XYXY+1 1 1 0 0 0 0 0 1 0 1 0 0 1 0 1 1 0 1 mmm 1 1 0 0 0 0 0 1 0 1 0 0 1 1 1 1 0 1 mmm 95 E:[HL],AE:[HL]-A, 1 1 0 0 0 0 0 1 0 1 0 0 0 0 1 1 0 1 mmm HLHL+1 E:[XY],AE:[XY]-A, 1 1 0 0 0 0 0 1 0 1 0 0 0 1 1 1 0 1 mmm XYXY+1 2 - 12 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set INSTRUCTION CODE MNEMONIC SUB cur,#i4 SUB [HL],#i4 SUB [XY],#i4 OPERATION cur,Acur-i4 [HL],A[HL]-i4 [XY],A[XY]-i4 WC FLAG 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Z C G 1 1 1 0 0 1 i3 i2 i1 i0 r7 r6 r5 r4 r3 r2 r1 r0 m m -- 1 1 0 0 0 0 0 0 1 0 1 0 1 0 i 3 i2 i1 i0 m m -- 1 1 0 0 0 0 0 0 1 0 1 0 1 1 i 3 i2 i1 i0 m m -- PAGE SUB E:[HL],#i4 E:[HL],AE:[HL]-i4 1 1 0 0 0 0 0 0 1 0 1 0 0 0 i3 i2 i1 i0 m m -- SUB E:[XY],#i4 E:[XY],AE:[XY]-i4 1 1 0 0 0 0 0 0 1 0 1 0 0 1 i3 i2 i1 i0 m m -- SUB [HL+],#i4 SUB [XY+],#i4 SUB E:[HL+],#i4 SUB E:[XY+],#i4 SBC sfr,A SBC cur,A SBC [HL],A SBC [XY],A SBC E:[HL],A SBC E:[XY],A SBC [HL+],A SBC [XY+],A SBC E:[HL+],A SBC E:[XY+],A SBCD sfr,A SBCD cur,A SBCD [HL],A [HL],A[HL]-i4, HLHL+1 [XY],A[XY]-i4, XYXY+1 E:[HL],AE:[HL]-i4, HLHL+1 E:[XY],AE:[XY]-i4, XYXY+1 sfr,Asfr-A-C cur,Acur-A-C 1 1 0 0 0 0 0 0 1 1 1 0 1 0 i3 i2 i1 i0 m m m 1 1 0 0 0 0 0 0 1 1 1 0 1 1 i3 i2 i1 i0 m m m 1 1 0 0 0 0 0 0 1 1 1 0 0 0 i 3 i2 i1 i0 m m m 1 1 0 0 0 0 0 0 1 1 1 0 0 1 i 3 i2 i1 i0 m m m 1 1 0 0 1 0 1 0 0 0 r7 r6 r5 r4 r3 r2 r1 r0 m m -- 1 1 0 0 1 1 1 0 0 0 r7 r6 r5 r4 r3 r2 r1 r0 m m -- 96 [HL],A[HL]-A-C 1 1 0 0 0 0 0 1 0 1 0 0 1 0 0 1 1 0 m m -- [XY],A[XY]-A-C 1 1 0 0 0 0 0 1 0 1 0 0 1 1 0 1 1 0 m m -- E:[HL],AE:[HL]-A-C 1 1 0 0 0 0 0 1 0 1 0 0 0 0 0 1 1 0 m m -- E:[XY],AE:[XY]-A-C 1 1 0 0 0 0 0 1 0 1 0 0 0 1 0 1 1 0 m m -- [HL],A[HL]-A-C, 1 1 0 0 0 0 0 1 0 1 0 0 1 0 1 1 1 0 mmm HLHL+1 [XY],A[XY]-A-C, 1 1 0 0 0 0 0 1 0 1 0 0 1 1 1 1 1 0 mmm XYXY+1 E:[HL],AE:[HL]-A-C, 1 1 0 0 0 0 0 1 0 1 0 0 0 0 1 1 1 0 mmm HLHL+1 E:[XY],AE:[XY]-A-C, 1 1 0 0 0 0 0 1 0 1 0 0 0 1 1 1 1 0 mmm XYXY+1 sfr,Adecimal adjustment 1 1 0 0 1 0 1 0 0 1 r7 r6 r5 r4 r3 r2 r1 r0 m m -- {sfr-A-C} cur,Adecimal adjustment 1 1 0 0 1 1 1 0 0 1 r7 r6 r5 r4 r3 r2 r1 r0 m m -- 92 {cur-A-C} [HL],Adecimal adjustment 1 1 0 0 0 0 0 1 0 1 0 0 1 0 0 1 1 1 mm-- {[HL]-A-C} 91 2 - 13 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set INSTRUCTION CODE MNEMONIC SBCD [XY],A SBCD E:[HL],A SBCD E:[XY],A OPERATION WC FLAG 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Z C G PAGE [XY],Adecimal adjustment 1 1 0 0 0 0 0 1 0 1 0 0 1 1 0 1 1 1 mm-- {[XY]-A-C} E:[HL],Adecimal adjustment {E:[HL]-A-C} E:[XY],Adecimal adjustment {E:[XY]-A-C} [HL],Adecimal adjustment {[HL]-A-C}, HLHL+1 [XY],Adecimal adjustment {[XY]-A-C}, XYXY+1 1 1 0 0 0 0 0 1 0 1 0 0 0 0 0 1 1 1 mm-- 1 1 0 0 0 0 0 1 0 1 0 0 0 1 0 1 1 1 mm-- SBCD [HL+],A 1 1 0 0 0 0 0 1 0 1 0 0 1 0 1 1 1 1 mmm 92 1 1 0 0 0 0 0 1 0 1 0 0 1 1 1 1 1 1 mmm SBCD [XY+],A E:[HL],Adecimal SBCD E:[HL+],A adjustment {E:[HL]-A-C}, HLHL+1 E:[XY],Adecimal SBCD E:[XY+],A adjustment {E:[XY]-A-C}, XYXY+1 SBCJ cur,n SBCJ [HL],n SBCJ [XY],n SBCJ E:[HL],n SBCJ E:[XY],n SBCJ [HL+],n SBCJ [XY+],n SBCJ E:[HL+],n SBCJ E:[XY+],n cur,Abase-n adjustment {cur-C} 1 1 0 0 0 0 0 1 0 1 0 0 0 0 1 1 1 1 mmm 1 1 0 0 0 0 0 1 0 1 0 0 0 1 1 1 1 1 mmm 1 1 0 0 0 1 1 n2 n1 n0 r7 r6 r5 r4 r3 r2 r1 r0 m m -- [HL],Abase-n adjustment 1 1 0 0 0 0 0 1 1 0 0 0 1 0 1 n2 n1 n0 m m -- {[HL]-C} [XY],Abase-n adjustment 1 1 0 0 0 0 0 1 1 0 0 0 1 1 1 n2 n1 n0 m m -- {[XY]-C} E:[HL],Abase-n adjustment 1 1 0 0 0 0 0 1 1 0 0 0 0 0 1 n2 n1 n0 m m -- {E:[HL]-C} E:[XY],Abase-n adjustment 1 1 0 0 0 0 0 1 1 0 0 0 0 1 1 n2 n1 n0 m m -- {E:[XY]-C} [HL],Abase-n adjustment 1 1 0 0 0 0 0 1 1 1 0 0 1 0 1 n2 n1 n0 m m m {[HL]-C},HLHL+1 [XY],Abase-n adjustment 1 1 0 0 0 0 0 1 1 1 0 0 1 1 1 n2 n1 n0 m m m {[XY]-C},XYXY+1 E:[HL],Abase-n adjustment 1 1 0 0 0 0 0 1 1 1 0 0 0 0 1 n2 n1 n0 m m m {E:[HL]-C},HLHL+1 E:[XY],Abase-n adjustment 1 1 0 0 0 0 0 1 1 1 0 0 0 1 1 n2 n1 n0 m m m {E:[XY]-C},XYXY+1 93 2 - 14 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set l Comparison Instructions INSTRUCTION CODE MNEMONIC CMP sfr,A CMP cur,A CMP [HL],A CMP [XY],A CMP E:[HL],A CMP E:[XY],A CMP [HL+],A CMP [XY+],A OPERATION sfr-A cur-A [HL]-A [XY]-A E:[HL]-A E:[XY]-A [HL]-A,HLHL+1 [XY]-A,XYXY+1 WC FLAG PAGE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Z C G 1 1 0 0 1 0 1 0 1 0 r7 r6 r5 r4 r3 r2 r1 r0 m m -- 1 1 0 0 1 1 1 0 1 0 r7 r6 r5 r4 r3 r2 r1 r0 m m -- 1 1 0 0 0 0 0 1 0 0 0 0 1 0 0 1 0 0 mm-- 1 1 0 0 0 0 0 1 0 0 0 0 1 1 0 1 0 0 mm-- 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 mm-- 1 1 0 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 mm-- 1 1 0 0 0 0 0 1 0 0 0 0 1 0 1 1 0 0 mmm 1 1 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 mmm 1 1 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 mmm 1 1 0 0 0 0 0 1 0 0 0 0 0 1 1 1 0 0 mmm 1 1 1 0 1 0 i3 i2 i1 i0 r7 r6 r5 r4 r3 r2 r1 r0 m m -- 1 1 0 0 0 0 0 1 1 0 1 0 1 0 i3 i2 i1 i0 m m -- 1 1 0 0 0 0 0 1 1 0 1 0 1 1 i3 i2 i1 i0 m m -- 1 1 0 0 0 0 0 1 1 0 1 0 0 0 i3 i2 i1 i0 m m -- 1 1 0 0 0 0 0 1 1 0 1 0 0 1 i3 i2 i1 i0 m m -- 1 1 0 0 0 0 0 1 1 1 1 0 1 0 i3 i2 i1 i0 m m m 1 1 0 0 0 0 0 1 1 1 1 0 1 1 i3 i2 i1 i0 m m m 49 48 CMP E:[HL+],A E:[HL]-A,HLHL+1 CMP E:[XY+],A E:[XY]-A,XYXY+1 CMP cur,#i4 CMP [HL],#i4 CMP [XY],#i4 cur-i4 [HL]-i4 [XY]-i4 CMP E:[HL],#i4 E:[HL]-i4 CMP E:[XY],#i4 E:[XY]-i4 CMP [HL+],#i4 CMP [XY+],#i4 [HL]-i4,HLHL+1 [XY]-i4,XYXY+1 CMP E:[HL+],#i4 E:[HL]-i4,HLHL+1 1 1 0 0 0 0 0 1 1 1 1 0 0 0 i3 i2 i1 i0 m m m CMP E:[XY+],#i4 E:[XY]-i4,XYXY+1 1 1 0 0 0 0 0 1 1 1 1 0 0 1 i3 i2 i1 i0 m m m 2 - 15 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set l Logical Operation Instructions INSTRUCTION CODE MNEMONIC AND sfr,A AND cur,A AND [HL],A AND [XY],A AND E:[HL],A AND E:[XY],A AND [HL+],A AND [XY+],A AND E:[HL+],A AND E:[XY+],A AND cur,#i4 AND [HL],#i4 AND [XY],#i4 OPERATION sfr,Asfr cur,Acur [HL],A[HL] [XY],A[XY] A A WC FLAG PAGE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Z C G 1 1 0 0 1 0 1 0 1 1 r7 r6 r5 r4 r3 r2 r1 r0 m -- -- 1 1 0 0 1 1 1 0 1 1 r7 r6 r5 r4 r3 r2 r1 r0 m -- -- A 1 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 m---- A 1 1 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 1 m---- E:[HL],AE:[HL] A 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 m -- -- E:[XY],AE:[XY] A 1 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 1 m -- -- [HL],A[HL] HLHL+1 [XY],A[XY] XYXY+1 A, A, 39 1 1 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 1 m--m 1 1 0 0 0 0 0 1 0 0 0 0 1 1 1 0 0 1 m--m E:[HL],AE:[HL] A, 1 1 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 1 m--m HLHL+1 E:[XY],AE:[XY] A, 1 1 0 0 0 0 0 1 0 0 0 0 0 1 1 0 0 1 m--m XYXY+1 cur,Acur [HL],A[HL] [XY],A[XY] i4 1 1 0 1 0 1 i3 i2 i1 i0 r7 r6 r5 r4 r3 r2 r1 r0 m -- -- i4 1 1 0 0 0 0 0 1 0 0 0 1 1 0 i3 i2 i1 i0 m -- -- i4 1 1 0 0 0 0 0 1 0 0 0 1 1 1 i3 i2 i1 i0 m -- -- AND E:[HL],#i4 E:[HL],AE:[HL] i4 1 1 0 0 0 0 0 1 0 0 0 1 0 0 i3 i2 i1 i0 m -- -- AND E:[XY],#i4 E:[XY],AE:[XY] i4 1 1 0 0 0 0 0 1 0 0 0 1 0 1 i3 i2 i1 i0 m -- -- AND [HL+],#i4 AND [XY+],#i4 AND E:[HL+],#i4 AND E:[XY+],#i4 [HL],A[HL] HLHL+1 [XY],A[XY] XYXY+1 i4, i4, 1 1 0 0 0 0 0 1 0 1 0 1 1 0 i3 i2 i1 i0 m -- m 1 1 0 0 0 0 0 1 0 1 0 1 1 1 i3 i2 i1 i0 m -- m 40 E:[HL],AE:[HL] i4, 1 1 0 0 0 0 0 1 0 1 0 1 0 0 i3 i2 i1 i0 m -- m HLHL+1 E:[XY],AE:[XY] i4, 1 1 0 0 0 0 0 1 0 1 0 1 0 1 i3 i2 i1 i0 m -- m XYXY+1 2 - 16 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set INSTRUCTION CODE MNEMONIC OR sfr,A OR cur,A OR [HL],A OR [XY],A OR E:[HL],A OR E:[XY],A OR [HL+],A OR [XY+],A OR E:[HL+],A OR E:[XY+],A OR cur,#i4 OR [HL],#i4 OR [XY],#i4 OR E:[HL],#i4 OR E:[XY],#i4 OR [HL+],#i4 OR [XY+],#i4 OR E:[HL+],#i4 OR E:[XY+],#i4 OPERATION sfr,Asfr cur,Acur [HL],A[HL] [XY],A[XY] A A WC FLAG PAGE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Z C G 1 1 0 0 1 0 1 1 0 0 r7 r6 r5 r4 r3 r2 r1 r0 m -- -- 1 1 0 0 1 1 1 1 0 0 r7 r6 r5 r4 r3 r2 r1 r0 m -- -- A 1 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 m---- A 1 1 0 0 0 0 0 1 0 0 0 0 1 1 0 0 1 0 m---- 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 m---- 1 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 1 0 m---- 1 1 0 0 0 0 0 1 0 0 0 0 1 0 1 0 1 0 m--m 1 1 0 0 0 0 0 1 0 0 0 0 1 1 1 0 1 0 m--m 82 E:[HL],AE:[HL] A E:[XY],AE:[XY] A [HL],A[HL] HLHL+1 [XY],A[XY] XYXY+1 A, A, E:[HL],AE:[HL] A, 1 1 0 0 0 0 0 1 0 0 0 0 0 0 1 0 1 0 m--m HLHL+1 E:[XY],AE:[XY] A, 1 1 0 0 0 0 0 1 0 0 0 0 0 1 1 0 1 0 m--m XYXY+1 cur,Acur [HL],A[HL] [XY],A[XY] i4 1 1 0 1 1 0 i3 i2 i1 i0 r7 r6 r5 r4 r3 r2 r1 r0 m -- -- i4 1 1 0 0 0 0 0 0 1 0 0 1 1 0 i3 i2 i1 i0 m -- -- i4 1 1 0 0 0 0 0 0 1 0 0 1 1 1 i3 i2 i1 i0 m -- -- E:[HL],AE:[HL] i4 1 1 0 0 0 0 0 0 1 0 0 1 0 0 i3 i2 i1 i0 m -- -- E:[XY],AE:[XY] i4 1 1 0 0 0 0 0 0 1 0 0 1 0 1 i3 i2 i1 i0 m -- -- [HL],A[HL] HLHL+1 [XY],A[XY] XYXY+1 i4, i4, 1 1 0 0 0 0 0 0 1 1 0 1 1 0 i3 i2 i1 i0 m -- m 1 1 0 0 0 0 0 0 1 1 0 1 1 1 i3 i2 i1 i0 m -- m 83 E:[HL],AE:[HL] i4, 1 1 0 0 0 0 0 0 1 1 0 1 0 0 i3 i2 i1 i0 m -- m HLHL+1 E:[XY],AE:[XY] i4, 1 1 0 0 0 0 0 0 1 1 0 1 0 1 i3 i2 i1 i0 m -- m XYXY+1 2 - 17 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set INSTRUCTION CODE MNEMONIC XOR sfr,A XOR cur,A XOR [HL],A XOR [XY],A XOR E:[HL],A XOR E:[XY],A XOR [HL+],A XOR [XY+],A XOR E:[HL+],A XOR E:[XY+],A XOR cur,#i4 XOR [HL],#i4 XOR [XY],#i4 OPERATION sfr,Asfr"A cur,Acur"A [HL],A[HL]"A [XY],A[XY]"A E:[HL],AE:[HL]"A E:[XY],AE:[XY]"A WC FLAG PAGE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Z C G 1 1 0 0 1 0 1 1 0 1 r7 r6 r5 r4 r3 r2 r1 r0 m -- -- 1 1 0 0 1 1 1 1 0 1 r7 r6 r5 r4 r3 r2 r1 r0 m -- -- 1 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 1 m---- 1 1 0 0 0 0 0 1 0 0 0 0 1 1 0 0 1 1 m---- 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 m---- 1 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 1 1 m---- 98 [HL],A[HL]"A,HL 1 1 0 0 0 0 0 1 0 0 0 0 1 0 1 0 1 1 m--m HL+1 [XY],A[XY]"A,XY 1 1 0 0 0 0 0 1 0 0 0 0 1 1 1 0 1 1 m--m XY+1 E:[HL],AE:[HL]"A, HLHL+1 E:[XY],AE:[XY]"A, XYXY+1 cur,Acur"i4 [HL],A[HL]"i4 [XY],A[XY]"i4 1 1 0 0 0 0 0 1 0 0 0 0 0 0 1 0 1 1 m--m 1 1 0 0 0 0 0 1 0 0 0 0 0 1 1 0 1 1 m--m 1 1 0 1 1 1 i3 i2 i1 i0 r7 r6 r5 r4 r3 r2 r1 r0 m -- -- 1 1 0 0 0 0 0 0 0 0 0 1 1 0 i3 i2 i1 i0 m -- -- 1 1 0 0 0 0 0 0 0 0 0 1 1 1 i3 i2 i1 i0 m -- -- 1 1 0 0 0 0 0 0 0 0 0 1 0 0 i3 i2 i1 i0 m -- -- 1 1 0 0 0 0 0 0 0 0 0 1 0 1 i3 i2 i1 i0 m -- -- XOR E:[HL],#i4 E:[HL],AE:[HL]"i4 XOR E:[XY],#i4 E:[XY],AE:[XY]"i4 XOR [HL],#i4 XOR [XY+],#i4 XOR E:[HL+],#i4 XOR E:[XY+],#i4 [HL],A[HL]"i4, 1 1 0 0 0 0 0 0 0 1 0 1 1 0 i3 i2 i1 i0 m -- m HLHL+1 [XY],A[XY]"i4, 1 1 0 0 0 0 0 0 0 1 0 1 1 1 i3 i2 i1 i0 m -- m XYXY+1 E:[HL],AE:[HL]"i4, HLHL+1 E:[XY],AE:[XY]"i4, XYXY+1 1 1 0 0 0 0 0 0 0 1 0 1 0 0 i3 i2 i1 i0 m -- m 1 1 0 0 0 0 0 0 0 1 0 1 0 1 i3 i2 i1 i0 m -- m 99 2 - 18 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set l Mask Operation Instructions INSTRUCTION CODE MNEMONIC MMOV [HL]#m,A.n MMOV [XY]#m,A.n MMOV E:[HL]#m,A.n MMOV E:[XY]#m,A.n MTST sfr,A MTST cur,A MTST [HL],A MTST [XY],A MTST E:[HL],A MTST E:[XY],A OPERATION WC FLAG PAGE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Z C G Transfer A.n to all bits not 1 masked by [HL]#mA[HL] Transfer A.n to all bits not 1 masked by [XY]#mA[HL] Transfer A.n to all bits not 1 masked by [HL]#mA[HL] Transfer A.n to all bits not 1 masked by [XY]#mA[HL] 1 0 0 0 0 0 n1 n0 0 1 1 1 0 m3 m2 m1 m0 m -- -- 1 0 0 0 0 0 n1 n0 0 1 1 1 1 m3 m2 m1 m0 m -- -- 62 1 0 0 0 0 0 n1 n0 0 1 1 0 0 m3 m2 m1 m0 m -- -- 1 0 0 0 0 0 n1 n0 0 1 1 0 1 m3 m2 m1 m0 m -- -- Test all bits not masked sfr A Test all bits not masked cur A Test all bits not masked by [HL] A Test all bits not masked by [XY] A Test all bits not masked by E:[HL] A Test all bits not masked by E:[XY] A Test all bits not masked by [HL] A, HLHL+1 Test all bits not masked by [XY] A, XYXY+1 1 1 0 0 1 0 1 1 1 1 r7 r6 r5 r4 r3 r2 r1 r0 m -- -- 1 1 0 0 1 1 1 1 1 1 r7 r6 r5 r4 r3 r2 r1 r0 m -- -- 1 1 0 0 0 0 0 1 0 0 0 0 1 0 0 1 0 1 m---- 1 1 0 0 0 0 0 1 0 0 0 0 1 1 0 1 0 1 m---- 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 1 m---- 1 1 0 0 0 0 0 1 0 0 0 0 0 1 0 1 0 1 m---- 79 MTST [HL+],A 1 1 0 0 0 0 0 1 0 0 0 0 1 0 1 1 0 1 m--m MTST [XY+],A 1 1 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 1 m--m Test all bits MTST E:[HL+],A not masked by A E:[HL], HLHL+1 1 1 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 1 m--m Test all bits MTST E:[XY+],A not masked by A E:[XY] , 1 1 0 0 0 0 0 1 0 0 0 0 0 1 1 1 0 1 m -- m XYXY+1 2 - 19 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set INSTRUCTION CODE MNEMONIC MTST cur,#m MTST [HL],#m MTST [XY],#m MTST E:[HL],#m MTST E:[XY],#m OPERATION Test all bits not masked by cur #m Test all bits not masked by [HL] #m Test all bits not masked by [XY] #m WC FLAG PAGE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Z C G 1 1 1 0 1 1 m3 m2 m1 m0 r7 r6 r5 r4 r3 r2 r1 r0 m -- -- 1 1 0 0 0 0 0 1 0 0 1 0 1 0 m3 m2 m1 m0 m -- -- 1 1 0 0 0 0 0 1 0 0 1 0 1 1 m3 m2 m1 m0 m -- -- Test all bits 1 1 0 0 0 0 0 1 0 0 1 0 0 0 m3 m2 m1 m0 m -- -- not masked by E:[HL] #m Test all bits 1 1 0 0 0 0 0 1 0 0 1 0 0 1 m3 m2 m1 m0 m -- -- not masked by E:[XY] #m 80 Test all bits MTST [HL+],#m not masked by [HL] #m, 1 1 0 0 0 0 0 1 0 1 1 0 1 0 m3 m2 m1 m0 m -- m HLHL+1 Test all bits MTST [XY+],#m not masked by [XY] #m, 1 1 0 0 0 0 0 1 0 1 1 0 1 1 m3 m2 m1 m0 m -- m XYXY+1 MTST E:[HL+], #m MTST E:[XY+], #m Test all bits not masked by E:[HL] #m, 1 1 0 0 0 0 0 1 0 1 1 0 0 0 m3 m2 m1 m0 m -- m HLHL+1 Test all bits not masked by E:[XY] #m, 1 1 0 0 0 0 0 1 0 1 1 0 0 1 m3 m2 m1 m0 m -- m XYXY+1 2 - 20 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set INSTRUCTION CODE MNEMONIC OPERATION WC Clear all bit MCLR cur,#m not masked by cur #m, Acur Clear all bit MCLR [HL],#m not masked by [HL] #m,A[HL] Clear all bit MCLR [XY],#m not masked by [XY] #m,A[XY] FLAG PAGE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Z C G 1 1 0 1 0 1 m3 m2 m1 m0 r7 r6 r5 r4 r3 r2 r1 r0 m -- -- 1 1 0 0 0 0 0 1 0 0 0 1 1 0 m3 m2 m1 m0 m -- -- 1 1 0 0 0 0 0 1 0 0 0 1 1 1 m3 m2 m1 m0 m -- -- Clear all bit MCLR E:[HL],#m not masked by E:[HL] 1 1 0 0 0 0 0 1 0 0 0 1 0 0 m3 m2 m1 m0 m -- -- #m,AE:[HL] Clear all bit MCLR E:[XY],#m not masked by E:[XY] 1 1 0 0 0 0 0 1 0 0 0 1 0 1 m3 m2 m1 m0 m -- -- #m,AE:[XY] Clear all bit 1 1 0 0 0 0 0 1 0 1 0 1 1 0 m3 m2 m1 m0 m -- m MCLR [HL+],#m not masked by [HL] #m,A[HL],HLHL+1 Clear all bit MCLR [XY+],#m not masked by [XY] 1 1 0 0 0 0 0 1 0 1 0 1 1 1 m3 m2 m1 m0 m -- m #m,A[XY],XYXY+1 Clear all bit MCLR E:[HL+], not masked by E:[HL] 1 1 0 0 0 0 0 1 0 1 0 1 0 0 m3 m2 m1 m0 m -- m #m #m,AE:[HL],HLHL+1 Clear all bit MCLR E:[XY+], not masked by E:[XY] 1 1 0 0 0 0 0 1 0 1 0 1 0 1 m3 m2 m1 m0 m -- m #m #m,AE:[XY],XYXY+1 61 2 - 21 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set INSTRUCTION CODE MNEMONIC OPERATION Set all bits not masked by cur #m, Acur WC FLAG PAGE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Z C G MSET cur,#m 1 1 0 1 1 0 m3 m2 m1 m0 r7 r6 r5 r4 r3 r2 r1 r0 m -- -- MSET [HL],#m Set all bits not masked by [HL] #m, 1 1 0 0 0 0 0 0 1 0 0 1 1 0 m3 m2 m1 m0 m -- -- A[HL] Set all bits not masked by [XY] #m, 1 1 0 0 0 0 0 0 1 0 0 1 1 1 m3 m2 m1 m0 m -- -- A[XY] MSET [XY],#m Set all bits MSET E:[HL],#m not masked by E:[HL] #m, 1 1 0 0 0 0 0 0 1 0 0 1 0 0 m3 m2 m1 m0 m -- -- AE:[HL] Set all bits MSET E:[XY],#m not masked by E:[XY] #m, 1 1 0 0 0 0 0 0 1 0 0 1 0 1 m3 m2 m1 m0 m -- -- AE:[XY] Set all bits MSET [HL+],#m not masked by [HL] #m, 1 1 0 0 0 0 0 0 1 1 0 1 1 0 m3 m2 m1 m0 m -- m A[HL],HLHL+1 Set all bits MSET [XY+],#m not masked by [XY] #m, 1 1 0 0 0 0 0 0 1 1 0 1 1 1 m3 m2 m1 m0 m -- m A[XY],XYXY+1 MSET E:[HL+], #m MSET E:[XY+], #m Set all bits not masked by E:[HL] #m, 1 1 0 0 0 0 0 0 1 1 0 1 0 0 m3 m2 m1 m0 m -- m AE:[HL],HLHL+1 Set all bits not masked by E:[XY] #m, 1 1 0 0 0 0 0 0 1 1 0 1 0 1 m3 m2 m1 m0 m -- m AE:[XY],XYXY+1 78 2 - 22 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set INSTRUCTION CODE MNEMONIC OPERATION WC Invert all bits MNOT cur,#m not masked by cur #m, Acur FLAG PAGE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Z C G 1 1 0 1 1 1 m3 m2 m1 m0 r7 r6 r5 r4 r3 r2 r1 r0 m -- -- Invert all bits MNOT [HL],#m not masked by [HL] #m, 1 1 0 0 0 0 0 0 0 0 0 1 1 0 m3 m2 m1 m0 m -- -- A[HL] Invert all bits MNOT [XY],#m not masked by [XY] #m, 1 1 0 0 0 0 0 0 0 0 0 1 1 1 m3 m2 m1 m0 m -- -- A[XY] Invert all bits MNOT E:[HL],#m not masked by E:[HL] #m, 1 1 0 0 0 0 0 0 0 0 0 1 0 0 m3 m2 m1 m0 m -- -- AE:[HL] Invert all bits MNOT E:[XY],#m not masked by E:[XY] #m, 1 1 0 0 0 0 0 0 0 0 0 1 0 1 m3 m2 m1 m0 m -- -- 63 AE:[XY] Invert all bits MNOT [HL+],#m not masked by [HL] #m, 1 1 0 0 0 0 0 0 0 1 0 1 1 0 m3 m2 m1 m0 m -- m A[HL],HLHL+1 Invert all bits MNOT [XY+],#m not masked by [XY] #m, 1 1 0 0 0 0 0 0 0 1 0 1 1 1 m3 m2 m1 m0 m -- m A[XY],XYXY+1 Invert all bits MNOT E:[HL+], not masked by E:[HL] #m, 1 1 0 0 0 0 0 0 0 1 0 1 0 0 m m m m m -- m 3210 #m AE:[HL],HLHL+1 Invert all bits MNOT E:[XY+], not masked by E:[XY] #m, 1 1 0 0 0 0 0 0 0 1 0 1 0 1 m3 m2 m1 m0 m -- m #m AE:[XY],XYXY+1 2 - 23 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set l Bit Operation Instructions INSTRUCTION CODE MNEMONIC BMOV [HL].n,A.n BMOV [XY].n,A.n OPERATION WC FLAG PAGE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Z C G [HL].nA.n,A[HL] 1 1 0 0 0 0 0 n1 n0 0 1 1 1 0 r3 r2 r1 r0 m -- -- [XY].nA.n,A[XY] 1 1 0 0 0 0 0 n1 n0 0 1 1 1 1 r3 r2 r1 r0 m -- -- 43 BMOV E:[HL].n,A.n E:[HL].nA.n,AE:[HL] 1 1 0 0 0 0 0 n1 n0 0 1 1 0 0 r3 r2 r1 r0 m -- -- BMOV E:[XY].n,A.n E:[XY].nA.n,AE:[XY] 1 1 0 0 0 0 0 n1 n0 0 1 1 0 1 r3 r2 r1 r0 m -- -- BTST cur.n BTST [HL].n BTST [XY].n BTST E:[HL].n BTST E:[XY].n BTST [HL+].n BTST [XY+].n BTST E:[HL+].n BTST E:[XY+].n BCLR cur.n BCLR [HL].n BCLR [XY].n BCLR E:[HL].n BCLR E:[XY].n BCLR [HL+].n BCLR [XY+].n BCLR E:[HL+].n BCLR E:[XY+].n cur.n bit test [HL].n bit test [XY].n bit test E:[HL].n bit test E:[XY].n bit test [HL].n, bit test HLHL+1 [XY].n, bit test XYXY+1 E:[HL].n, bit test HLHL+1 E:[XY].n, bit test XYXY+1 cur.n0,Acur [HL].n0,A[HL] [XY].n0,A[XY] 1 1 1 0 1 1 n3 n2 n1 n0 r7 r6 r5 r4 r3 r2 r1 r0 m -- -- 1 1 0 0 0 0 0 1 0 0 1 0 1 0 n3 n2 n1 n0 m -- -- 1 1 0 0 0 0 0 1 0 0 1 0 1 1 n3 n2 n1 n0 m -- -- 1 1 0 0 0 0 0 1 0 0 1 0 0 0 n3 n2 n1 n0 m -- -- 1 1 0 0 0 0 0 1 0 0 1 0 0 1 n3 n2 n1 n0 m -- -- 1 1 0 0 0 0 0 1 0 1 1 0 1 0 n3 n2 n1 n0 m -- m 1 1 0 0 0 0 0 1 0 1 1 0 1 1 n3 n2 n1 n0 m -- m 1 1 0 0 0 0 0 1 0 1 1 0 0 0 n3 n2 n1 n0 m -- m 1 1 0 0 0 0 0 1 0 1 1 0 0 1 n3 n2 n1 n0 m -- m 1 1 0 1 0 1 n3 n2 n1 n0 r7 r6 r5 r4 r3 r2 r1 r0 m -- -- 1 1 0 0 0 0 0 1 0 0 0 1 1 0 n3 n2 n1 n0 m -- -- 1 1 0 0 0 0 0 1 0 0 0 1 1 1 n3 n2 n1 n0 m -- -- 46 E:[HL].n0,AE:[HL] 1 1 0 0 0 0 0 1 0 0 0 1 0 0 n3 n2 n1 n0 m -- -- E:[XY].n0,AE:[XY] 1 1 0 0 0 0 0 1 0 0 0 1 0 1 n3 n2 n1 n0 m -- -- [HL].n0,A[HL], 1 1 0 0 0 0 0 1 0 1 0 1 1 0 n3 n2 n1 n0 m -- m HLHL+1 [XY].n0,A[XY], 1 1 0 0 0 0 0 1 0 1 0 1 1 1 n3 n2 n1 n0 m -- m XYXY+1 E:[HL].n0,AE:[HL], 1 1 0 0 0 0 0 1 0 1 0 1 0 0 n3 n2 n1 n0 m -- m HLHL+1 E:[XY].n0,AE:[XY], 1 1 0 0 0 0 0 1 0 1 0 1 0 1 n3 n2 n1 n0 m -- m XYXY+1 42 2 - 24 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set INSTRUCTION CODE MNEMONIC BSET cur.n BSET [HL].n BSET [XY].n BSET E:[HL].n BSET E:[XY].n BSET [HL+].n BSET [XY+].n BSET E:[HL+].n BSET E:[XY+].n BNOT cur.n BNOT [HL].n BNOT [XY].n BNOT E:[HL].n BNOT E:[XY].n BNOT [HL+].n BNOT [XY+].n BNOT E:[HL+].n BNOT E:[XY+].n OPERATION cur.n1,Acur [HL].n1,A[HL] [XY].n1,A[XY] WC FLAG 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Z C G PAGE 1 1 0 1 1 0 n3 n2 n1 n0 r7 r6 r5 r4 r3 r2 r1 r0 -- -- -- 1 1 0 0 0 0 0 0 1 0 0 1 1 0 n3 n2 n1 n0 -- -- -- 1 1 0 0 0 0 0 0 1 0 0 1 1 1 n3 n2 n1 n0 -- -- -- E:[HL].n1,AE:[HL] 1 1 0 0 0 0 0 0 1 0 0 1 0 0 n3 n2 n1 n0 -- -- -- E:[XY].n1,AE:[XY] 1 1 0 0 0 0 0 0 1 0 0 1 0 1 n3 n2 n1 n0 -- -- -- [HL].n1,A[HL], 1 1 0 0 0 0 0 0 1 1 0 1 1 0 n3 n2 n1 n0 -- -- m HLHL+1 [XY].n1,A[XY], 1 1 0 0 0 0 0 0 1 1 0 1 1 1 n3 n2 n1 n0 -- -- m XYXY+1 E:[HL].n1,AE:[HL], 1 1 0 0 0 0 0 0 1 1 0 1 0 0 n3 n2 n1 n0 -- -- m HLHL+1 E:[XY].n1,AE:[XY], 1 1 0 0 0 0 0 0 1 1 0 1 0 1 n3 n2 n1 n0 -- -- m XYXY+1 cur.ncur.n,Acur 1 1 0 1 1 1 n3 n2 n1 n0 r7 r6 r5 r4 r3 r2 r1 r0 m -- -- [HL].n[HL].n,A[HL] 1 1 0 0 0 0 0 0 0 0 0 1 1 0 n3 n2 n1 n0 m -- -- [XY].n[XY].n,A[XY] 1 1 0 0 0 0 0 0 0 0 0 1 1 1 n3 n2 n1 n0 m -- -- E:[HL].nE:[HL].n,A 1 1 0 0 0 0 0 0 0 0 0 1 0 0 n3 n2 n1 n0 m -- -- E:[HL] E:[XY].nE:[XY].n,A 1 1 0 0 0 0 0 0 0 0 0 1 0 1 n3 n2 n1 n0 m -- -- E:[XY] [HL].n[HL].n,A[HL], 1 1 0 0 0 0 0 0 0 1 0 1 1 0 n3 n2 n1 n0 m -- m HLHL+1 [XY].n[XY].n,A[XY], 1 1 0 0 0 0 0 0 0 1 0 1 1 1 n3 n2 n1 n0 m -- m XYXY+1 E:[HL].nE:[HL].n,A 1 1 0 0 0 0 0 0 0 1 0 1 0 0 n3 n2 n1 n0 m -- m E:[HL],HLHL+1 E:[XY].nE:[XY].n,A 1 1 0 0 0 0 0 0 0 1 0 1 0 1 n3 n2 n1 n0 m -- m E:[XY],XYXY+1 44 45 2 - 25 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set l ROM Table Reference Instructions INSTRUCTION CODE MNEMONIC MOVHB [HL], [RA] MOVHB [XY], [RA] OPERATION WC FLAG PAGE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Z C G [HL],[HL+1](RA)15~8 1 2 0 0 0 0 0 0 1 1 0 0 1 0 0 0 1 0 -- -- -- [XY],[XY+1](RA)15~8 1 2 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 0 -- -- -- MOVHB E:[HL], E:[HL],E:[HL+1] 1 2 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 ------ [RA] (RA)15~8 MOVHB E:[XY], E:[XY],E:[XY+1] 1 2 0 0 0 0 0 0 1 1 0 0 0 1 0 0 1 0 ------ [RA] (RA)15~8 69 MOVHB [HL+], [RA] MOVHB [XY+], [RA] [HL],[HL+1](RA)15~8, 1 2 0 0 0 0 0 0 1 1 0 0 1 0 1 0 1 0 ----m HLHL+2 [XY],[XY+1](RA)15~8, 1 2 0 0 0 0 0 0 1 1 0 0 1 1 1 0 1 0 ----m XYXY+2 MOVHB E:[HL+], E:[HL],E:[HL+1] 1 2 0 0 0 0 0 0 1 1 0 0 0 0 1 0 1 0 ----m [RA] (RA)15~8,HLHL+2 MOVHB E:[XY+], E:[XY],E:[XY+1] 1 2 0 0 0 0 0 0 1 1 0 0 0 1 1 0 1 0 ----m (RA)15~8,XYXY+2 [RA] MOVHB [HL], cadr16 MOVHB [XY], cadr16 [HL],[HL+1] (cadr16)15~8 [XY],[XY+1] (cadr16)15~8 23 23 0000001100100100 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0000001100110100 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 ------ ------ 0000001100000100 MOVHB E:[HL], E:[HL],E:[HL+1] ------ 23 cadr16 (cadr16)15~8 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0000001100010100 MOVHB E:[XY], E:[XY],E:[XY+1] ------ 23 cadr16 (cadr16)15~8 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 70 MOVHB [HL+], cadr16 MOVHB [XY+], cadr16 0000001100101100 [HL],[HL+1] ----m 23 (cadr16)15~8,HLHL+2 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0000001100111100 [XY],[XY+1] ----m 23 (cadr16)15~8,XYXY+2 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0000001100001100 MOVHB E:[HL+], E:[HL],E:[HL+1] ----m 23 cadr16 (cadr16)15~8,HLHL+2 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0000001100011100 MOVHB E:[XY+], E:[XY],E:[XY+1] ----m 23 cadr16 (cadr16)15~8,XYXY+2 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 2 - 26 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set INSTRUCTION CODE MNEMONIC MOVLB [HL], [RA] MOVLB [XY], [RA] OPERATION WC FLAG PAGE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Z C G [HL],[HL+1](RA)7~0 1 2 0 0 0 0 0 0 1 1 0 0 1 0 0 0 1 1 -- -- -- [XY],[XY+1](RA)7~0 1 2 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 -- -- -- MOVLB E:[HL], E:[HL],E:[HL+1] 1 2 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 ------ [RA] (RA)7~0 MOVLB E:[XY], E:[XY],E:[XY+1] 1 2 0 0 0 0 0 0 1 1 0 0 0 1 0 0 1 1 ------ [RA] (RA)7~0 MOVLB [HL+], [RA] MOVLB [XY+], [RA] [HL],[HL+1](RA)7~0, 1 2 0 0 0 0 0 0 1 1 0 0 1 0 1 0 1 1 ----m HLHL+2 [XY],[XY+1](RA)7~0, 1 2 0 0 0 0 0 0 1 1 0 0 1 1 1 0 1 1 ----m XYXY+2 1 2 0 0 0 0 0 0 1 1 0 0 0 0 1 0 1 1 ----m 1 2 0 0 0 0 0 0 1 1 0 0 0 1 1 0 1 1 ----m 23 23 0000001100100101 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0000001100110101 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 ------ ------ 71 MOVLB E:[HL+], E:[HL],E:[HL+1] [RA] (RA)7~0,HLHL+2 MOVLB E:[XY+], E:[XY],E:[XY+1] [RA] (RA)7~0,XYXY+2 MOVLB [HL], cadr16 MOVLB [XY], cadr16 [HL],[HL+1] (cadr16)7~0 [XY],[XY+1] (cadr16)7~0 0000001100000101 MOVLB E:[HL], E:[HL],E:[HL+1] ------ 23 cadr16 (cadr16)7~0 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0000001100010101 MOVLB E:[XY], E:[XY],E:[XY+1] ------ 23 cadr16 (cadr16)7~0 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 MOVLB [HL+], cadr16 MOVLB [XY+], cadr16 0000001100101101 [HL],[HL+1] ----m 23 (cadr16)7~0,HLHL+2 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0000001100111101 [XY],[XY+1] ----m 23 (cadr16)7~0,XYXY+2 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 72 0000001100001101 MOVLB E:[HL+], E:[HL],E:[HL+1] ----m 23 cadr16 (cadr16)7~0,HLHL+2 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0000001100011101 MOVLB E:[XY+], E:[XY],E:[XY+1] ----m 23 cadr16 (cadr16)7~0,XYXY+2 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 2 - 27 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set l External Memory Transfer Instructions INSTRUCTION CODE MNEMONIC MOVXB [HL], [RA] MOVXB [XY], [RA] OPERATION WC FLAG PAGE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Z C G [HL],[HL+1](RA) 1 2 0 0 0 0 0 0 1 1 0 0 1 0 0 1 1 0 -- -- -- [XY],[XY+1](RA) 1 2 0 0 0 0 0 0 1 1 0 0 1 1 0 1 1 0 -- -- -- MOVXB E:[HL], E:[HL],E:[HL+1](RA) 1 2 0 0 0 0 0 0 1 1 0 0 0 0 0 1 1 0 -- -- -- [RA] MOVXB E:[XY], E:[XY],E:[XY+1](RA) 1 2 0 0 0 0 0 0 1 1 0 0 0 1 0 1 1 0 -- -- -- [RA] MOVXB [HL+], [RA] MOVXB [XY+], [RA] [HL],[HL+1](RA), 1 2 0 0 0 0 0 0 1 1 0 0 1 0 1 1 1 0 ----m HLHL+2 [XY],[XY+1](RA), 1 2 0 0 0 0 0 0 1 1 0 0 1 1 1 1 1 0 ----m XYXY+2 73 MOVXB E:[HL+], E:[HL],E:[HL+1](RA), 1 2 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 0 ----m [RA] HLHL+2 MOVXB E:[XY+], E:[XY],E:[XY+1](RA), 1 2 0 0 0 0 0 0 1 1 0 0 0 1 1 1 1 0 ----m [RA] XYXY+2 MOVXB [RA], [HL] MOVXB [RA], [XY] MOVXB [RA], E:[HL] MOVXB [RA], E:[XY] MOVXB [RA], [HL+] MOVXB [RA], [XY+] MOVXB [RA], E:[HL+] MOVXB [RA], E:[XY+] (RA)[HL],[HL+1] 1 3 0 0 0 0 0 0 1 1 0 0 1 0 0 1 1 1 -- -- -- (RA)[XY],[XY+1] 1 3 0 0 0 0 0 0 1 1 0 0 1 1 0 1 1 1 -- -- -- (RA)E:[HL],E:[HL+1] 1 3 0 0 0 0 0 0 1 1 0 0 0 0 0 1 1 1 -- -- -- (RA)E:[XY],E:[XY+1] 1 3 0 0 0 0 0 0 1 1 0 0 0 1 0 1 1 1 -- -- -- (RA)[HL],[HL+1], 1 3 0 0 0 0 0 0 1 1 0 0 1 0 1 1 1 1 ----m HLHL+2 (RA)[XY],[XY+1], 1 3 0 0 0 0 0 0 1 1 0 0 1 1 1 1 1 1 ----m XYXY+2 (RA)E:[HL],E:[HL+1], 1 3 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 ----m HLHL+2 (RA)E:[XY],E:[XY+1], 1 3 0 0 0 0 0 0 1 1 0 0 0 1 1 1 1 1 ----m XYXY+2 75 2 - 28 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set INSTRUCTION CODE MNEMONIC MOVXB [HL], xadr16 MOVXB [XY], xadr16 OPERATION WC 0000001111100000 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0000001111110000 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 FLAG PAGE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Z C G ------ ------ [HL],[HL+1](xadr16) 2 3 [XY],[XY+1](xadr16) 2 3 0000001111000000 MOVXB E:[HL], E:[HL],E:[HL+1] ------ 23 xadr16 (xadr16) a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0000001111010000 MOVXB E:[XY], E:[XY],E:[XY+1] ------ 23 xadr16 (xadr16) a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 MOVXB [HL+], xadr16 MOVXB [XY+], xadr16 0000001111101000 [HL],[HL+1](xadr16), ----m 23 HLHL+2 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0000001111111000 [XY],[XY+1](xadr16), ----m 23 XYXY+2 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 74 0000001111001000 MOVXB E:[HL+], E:[HL],E:[HL+1] ----m 23 xadr16 (xadr16),HLHL+2 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0000001111011000 MOVXB E:[XY+], E:[XY],E:[XY+1] ----m 23 xadr16 (xadr16),XYXY+2 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0000001111100001 MOVXB xadr16, ------ (xadr16)[HL],[HL+1] 2 3 [HL] a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0000001111110001 MOVXB xadr16, ------ (xadr16)[XY],[XY+1] 2 3 [XY] a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0000001111000001 MOVXB xadr16, (xadr16)E:[HL],E: ------ 23 E:[HL] [HL+1] a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0000001111010001 MOVXB xadr16, (xadr16)E:[XY],E: ------ 23 E:[XY] [XY+1] a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0000001111101001 MOVXB xadr16, (xadr16)[HL],[HL+1], ----m 23 [HL+] HLHL+2 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0000001111111001 MOVXB xadr16, (xadr16)[XY],[XY+1], ----m 23 [XY+] XYXY+2 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0000001111001001 MOVXB xadr16, (xadr16)E:[HL],E: ----m 23 E:[HL+] [HL+1],HLHL+2 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0000001111011001 MOVXB xadr16, (xadr16)E:[XY],E: ----m 23 E:[XY+] [XY+1],XYXY+2 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 76 2 - 29 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set l Stack Operation Instructions INSTRUCTION CODE MNEMONIC PUSH HL PUSH XY POP HL POP XY OPERATION (RSP){FLAG,A,HL}, RSPRSP+1 WC FLAG PAGE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Z C G 1 2 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 -- -- -- 85 (RSP){CBR,EBR,XY}, 1 2 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 -- -- -- 86 RSPRSP+1 RSPRSP-1, {FLAG,A,HL}(RSP) 1 2 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 mmm 84 RSPRSP-1, 1 2 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 -- -- -- 85 {CBR,EBR,XY}(RSP) l Flag Operation Instructions INSTRUCTION CODE MNEMONIC FCLR G FCLR C FCLR Z FCLR FLAG FSET G FSET C FSET Z FSET FLAG OPERATION G0 C0 Z0 Z,C,G0 G1 C1 Z1 Z,C,G0 WC FLAG PAGE 53 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Z C G 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ----m 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 -- m -- 52 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 m -- -- 53 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 m -- -- 52 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 ----m 55 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 -- m -- 54 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 m -- -- 55 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 mmm 54 l Branch Instructions INSTRUCTION CODE MNEMONIC LJMP cadr16 JMP cadr12 SJMP radr8 JMP PC+A OPERATION PCcadr16 PC11~0cadr12 PCPC+A+1 WC 22 0000000000010100 0 0 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 FLAG 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Z C G PAGE -- -- -- 60 1 1 1 1 1 0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 -- -- -- 59 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 -- -- -- 59 PCNext PC+radr8 1 1 0 0 0 0 1 0 0 a7 1 a6 a5 a4 a3 a2 a1 a0 -- -- -- 94 2 - 30 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set l Conditional Branch Instructions INSTRUCTION CODE MNEMONIC BC radr8 BLT radr8 BNC radr8 BGE radr8 BZ radr8 BEQ radr8 BNZ radr8 BNE radr8 BLE radr8 BGT radr8 BNG radr8 OPERATION WC FLAG PAGE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Z C G if C=1 then 1 1 0 0 0 0 1 0 1 a7 0 a6 a5 a4 a3 a2 a1 a0 -- -- -- PCNext PC+radr8(<) if C=0 then 1 1 0 0 0 0 1 0 1 a7 1 a6 a5 a4 a3 a2 a1 a0 -- -- -- PCNext PC+radr8(>) = if Z=1 then 1 1 0 0 0 0 1 1 0 a7 0 a6 a5 a4 a3 a2 a1 a0 -- -- -- PCNext PC+radr8(=) if Z=0 then 1 1 0 0 0 0 1 1 0 a7 1 a6 a5 a4 a3 a2 a1 a0 -- -- -- PCNext PC+radr8() if (C=1) (Z=1) then 1 1 0 0 0 0 1 1 1 a7 0 a6 a5 a4 a3 a2 a1 a0 -- -- -- PCNext PC+radr8(> ) = if (C=0) (Z=0) then 1 1 0 0 0 0 1 1 1 a7 1 a6 a5 a4 a3 a2 a1 a0 -- -- -- PCNext PC+radr8(>) if G=0 then PCNext PC+radr8 1 1 0 0 0 0 1 0 0 a7 0 a6 a5 a4 a3 a2 a1 a0 -- -- -- 41 l Call/return Instructions INSTRUCTION CODE MNEMONIC LCAL cadr16 CAL cadr12 RT RTI RTNMI OPERATION WC FLAG PAGE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Z C G (SP)PC,PCcadr16, 2 2 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 -- -- -- 60 SPSP+1 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 (SP)PC,PC11~0 cadr12,SPSP+1 1 1 1 1 1 1 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 -- -- -- 47 PC(SP)+1,SPSP-1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 -- -- -- 89 PC(SP)+1,SPSP-1, 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 -- -- -- 89 MIE1 PC(SP)+1,SPSP-1 MIEPre-interrupt 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 ------ MIE state 90 2 - 31 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set l Control Instructions INSTRUCTION CODE MNEMONIC NOP HALT EI DI INCB HL INCB XY INCW RA MOV CBR,#i4 MOV EBR,#i4 MOV RA0,#i4 MOV RA1,#i4 MOV RA2,#i4 MOV RA3,#i4 MOV H,#i4 MOV L,#i4 MOV X,#i4 MOV Y,#i4 MSA cadr16 OPERATION NO OPERATION HALT CPU MIE1 MIE0 HLHL+1 XYXY+1 RARA+1 CBRi4 EBRi4 RA0i4 RA1i4 RA2i4 RA3i4 Hi4 Li4 Xi4 Yi4 WC FLAG PAGE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Z C G 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -- -- -- 81 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 -- -- -- 56 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 -- -- -- 51 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 -- -- -- 51 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 ----m 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 ----m 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 ----m 58 58 58 1 1 0 0 0 0 0 0 0 0 0 0 1 1 i3 i2 i1 i0 -- -- -- 68 1 1 0 0 0 0 0 0 0 0 0 0 1 0 i3 i2 i1 i0 -- -- -- 68 1 1 0 0 0 0 0 0 1 0 0 0 0 0 i3 i2 i1 i0 -- -- -- 68 1 1 0 0 0 0 0 0 1 0 0 0 0 1 i3 i2 i1 i0 -- -- -- 68 1 1 0 0 0 0 0 0 1 0 0 0 1 0 i3 i2 i1 i0 -- -- -- 68 1 1 0 0 0 0 0 0 1 0 0 0 1 1 i3 i2 i1 i0 -- -- -- 68 1 1 0 0 0 0 0 0 0 1 0 0 1 1 i3 i2 i1 i0 -- -- -- 68 1 1 0 0 0 0 0 0 0 1 0 0 1 0 i3 i2 i1 i0 -- -- -- 68 1 1 0 0 0 0 0 0 0 1 0 0 0 1 i3 i2 i1 i0 -- -- -- 68 1 1 0 0 0 0 0 0 0 1 0 0 0 0 i3 i2 i1 i0 -- -- -- 68 0000000000010110 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 -- -- -- 77 Melody output starts 2 3 2 - 32 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set 4. INSTRUCTION DESCRIPTIONS Instructions are detailed below. Refer to the following guides for information. obj obj Indicates items that can be described in the instruction operand Function Function Indicates the function using symbols Description Description Describes the instruction and gives precautions in use Flags Flags Indicates flags affected by execution of the instruction Codes/Cycles Codes/Cycles Indicates the instruction operand, instruction code and machine cycle 2 - 33 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set ADC obj, A obj (add data memory and accumulator with carry) For no post-increment: sfr, cur, [HL], [XY], E:[HL], E:[XY] For post-increment: [HL+], [XY+], E:[HL+], E:[XY+] Function obj, A obj + A + C (for post-increment) HL HL + 1 or XY XY + 1 Description The data memory specified by obj is added to the accumulator and the carry flag, and the results stored to data memory and the accumulator. For post-incremented operations, the HL or XY register is then incremented. Flags Flags affected by execution of this instruction Flag change conditions if obj + A + C = 0 then Z 1 else Z 0 if obj + A + C > 0FH then C 1 else C 0 (for post-increment) if HL + 1 = 0 or XY + 1 = 0 then G 1 else G 0 Codes/Cycles Operand sfr, A cur, A [HL], A [XY], A E:[HL], A E:[XY], A [HL+], A [XY+], A E:[HL+], A E:[XY+], A Instruction Code 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 9 0 0 0 0 0 0 0 0 0 0 8 1 1 1 1 1 1 1 1 1 1 7 r7 r7 0 0 0 0 0 0 0 0 6 r6 r6 0 0 0 0 0 0 0 0 5 r5 r5 1 1 0 0 1 1 0 0 4 r4 r4 0 1 0 1 0 1 0 1 3 r3 r3 0 0 0 0 1 1 1 1 2 r2 r2 0 0 0 0 0 0 0 0 1 r1 r1 1 1 1 1 1 1 1 1 0 r0 r0 1 1 1 1 1 1 1 1 Machine Cycle 1 1 1 1 1 1 1 1 1 1 Z C G m m m 2 - 34 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set ADCD obj, A obj (add data memory and accumulator decimal adjustment, with carry) For no post-increment: sfr, cur, [HL], [XY], E:[HL], E:[XY] For post-increment: [HL+], [XY+], E:[HL+], E:[XY+] Function obj, A decimal adjust {obj + A + C} (for post-increment) HL HL + 1 or XY XY + 1 Description The data memory specified by obj is added to the accumulator and the carry flag, and the results stored to data memory and the accumulator if 9 or less. If the results are greater than 9, the decimal adjustment 6H is added and the results stored to data memory and the accumulator. For post-incremented operations, the HL or XY register is then incremented. Flags Flags affected by execution of this instruction Flag change conditions if decimal adjustment = 0 then Z 1 else Z 0 if overflow results from operation C 1 else C 0 (for post-increment) if HL + 1 = 0 or XY + 1 = 0 then G 1 else G 0 Codes/Cycles Operand sfr, A cur, A [HL], A [XY], A E:[HL], A E:[XY], A [HL+], A [XY+], A E:[HL+], A E:[XY+], A Instruction Code 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 9 1 1 0 0 0 0 0 0 0 0 8 0 0 1 1 1 1 1 1 1 1 7 r7 r7 0 0 0 0 0 0 0 0 6 r6 r6 0 0 0 0 0 0 0 0 5 r5 r5 1 1 0 0 1 1 0 0 4 r4 r4 0 1 0 1 0 1 0 1 3 r3 r3 0 0 0 0 1 1 1 1 2 r2 r2 1 1 1 1 1 1 1 1 1 r1 r1 0 0 0 0 0 0 0 0 Machine Cycle 0 r0 r0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 Z C G m m m 2 - 35 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set ADCJ obj, n obj (data memory base-n adjustment addition, with carry) For no post-increment: cur, [HL], [XY], E:[HL], E:[XY] For post-increment: [HL+], [XY+], E:[HL+], E:[XY+] Function obj, A n adjust {obj + C} (n is even number from 2 to 16) (for post-increment) HL HL + 1 or XY XY + 1 Description The data memory specified by obj is added to the carry flag, the base-n results adjusted, and the results stored to data memory and the accumulator. If the results of base-n adjustment are greater than n, the adjustment (two's complement of n) is added. n is an even number from 2 to 16. For post-incremented operations, the HL or XY register is then incremented. Flags Flags affected by execution of this instruction Flag change conditions if base-n adjustment = 0 then Z 1 else Z 0 if overflow results from adjustment, or if n = 16 C 1 else C 0 (for post-increment) if HL + 1 = 0 or XY + 1 = 0 then G 1 else G 0 Codes/Cycles Operand cur, n [HL], n [XY], n E:[HL], n E:[XY], n [HL+], n [XY+], n E:[HL+], n E:[XY+], n Adjusted value n Values of n2 to n0 in instruction code Instruction Code 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1H n2 1 1 1 1 1 1 1 1 9 n1 1 1 1 1 1 1 1 1 4 2H 8 n0 0 0 0 0 1 1 1 1 7 r7 0 0 0 0 0 0 0 0 6 3H 6 r6 0 0 0 0 0 0 0 0 8 4H 5 r5 1 1 0 0 1 1 0 0 4 r4 0 1 0 1 0 1 0 1 10 5H 3 r3 0 0 0 0 0 0 0 0 2 r2 n2 n2 n2 n2 n2 n2 n2 n2 12 6H 1 r1 n1 n1 n1 n1 n1 n1 n1 n1 Machine Cycle 0 r0 n0 n0 n0 n0 n0 n0 n0 n0 14 7H 16 0H 1 1 1 1 1 1 1 1 1 Z C G m m m [Note] The adjusted value n and the values of n2 to n0 in the instruction code are as indicated below: 2 - 36 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set ADD obj, A obj (add data memory and accumulator) For no post-increment: sfr, cur, [HL], [XY], E:[HL], E:[XY] For post-increment: [HL+], [XY+], E:[HL+], E:[XY+] Function obj, A obj + A (for post-increment) HL HL + 1 or XY XY + 1 Description The data memory specified by obj is added to the accumulator, and the results stored to data memory and the accumulator. For post-incremented operations, the HL or XY register is then incremented. Flags Flags affected by execution of this instruction Flag change conditions if obj + A = 0 then Z 1 else Z 0 if obj + A > 0FH then C 1 else C 0 (for post-increment) if HL + 1 = 0 or XY + 1 = 0 then G 1 else G 0 Codes/Cycles Operand sfr, A cur, A [HL], A [XY], A E:[HL], A E:[XY], A [HL+], A [XY+], A E:[HL+], A E:[XY+], A Instruction Code 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 9 0 0 0 0 0 0 0 0 0 0 8 0 0 1 1 1 1 1 1 1 1 7 r7 r7 0 0 0 0 0 0 0 0 6 r6 r6 0 0 0 0 0 0 0 0 5 r5 r5 1 1 0 0 1 1 0 0 4 r4 r4 0 1 0 1 0 1 0 1 3 r3 r3 0 0 0 0 1 1 1 1 2 r2 r2 0 0 0 0 0 0 0 0 1 r1 r1 1 1 1 1 1 1 1 1 0 r0 r0 0 0 0 0 0 0 0 0 Machine Cycle 1 1 1 1 1 1 1 1 1 1 Z C G m m m 2 - 37 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set ADD obj, #i4 obj (add data memory and immediate data) For no post-increment: cur, [HL], [XY], E:[HL], E:[XY] For post-increment: [HL+], [XY+], E:[HL+], E:[XY+] Function obj, A obj + i4 (for post-increment) HL HL + 1 or XY XY + 1 Description The data memory specified by obj is added to immediate data i4, and the results stored to data memory and the accumulator. For post-incremented operations, the HL or XY register is then incremented. Flags Flags affected by execution of this instruction Flag change conditions if obj + i4 = 0 then Z 1 else Z 0 if obj + i4 > 0FH then C 1 else C 0 (for post-increment) if HL + 1 = 0 or XY + 1 = 0 then G 1 else G 0 Codes/Cycles Operand cur, #i4 [HL], #i4 [XY], #i4 E:[HL], #i4 E:[XY], #i4 [HL+], #i4 [XY+], #i4 E:[HL+], #i4 E:[XY+], #i4 Instruction Code 15 14 13 12 11 10 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i3 0 0 0 0 0 0 0 0 i2 0 0 0 0 0 0 0 0 9 i1 0 0 0 0 0 0 0 0 8 i0 0 0 0 0 1 1 1 1 7 r7 1 1 1 1 1 1 1 1 6 r6 0 0 0 0 0 0 0 0 5 r5 1 1 0 0 1 1 0 0 4 r4 0 1 0 1 0 1 0 1 3 r3 i3 i3 i3 i3 i3 i3 i3 i3 2 r2 i2 i2 i2 i2 i2 i2 i2 i2 1 r1 i1 i1 i1 i1 i1 i1 i1 i1 0 r0 i0 i0 i0 i0 i0 i0 i0 i0 Machine Cycle 1 1 1 1 1 1 1 1 1 Z C G m m m 2 - 38 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set AND obj, A obj (logical product of data memory and accumulator) For no post-increment: sfr, cur, [HL], [XY], E:[HL], E:[XY] For post-increment: [HL+], [XY+], E:[HL+], E:[XY+] Function obj, A obj ^ A (for post-increment) HL HL + 1 or XY XY + 1 Description The logical product of the data memory specified by obj and the accumulator is taken, and the results stored to data memory and the accumulator. For postincremented operations, the HL or XY register is then incremented. Flags Flags affected by execution of this instruction Flag change conditions if obj ^ A = 0 then Z 1 else Z 0 (for post-increment) if HL + 1 = 0 or XY + 1 = 0 then G 1 else G 0 Codes/Cycles Operand sfr, A cur, A [HL], A [XY], A E:[HL], A E:[XY], A [HL+], A [XY+], A E:[HL+], A E:[XY+], A Instruction Code 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 9 1 1 0 0 0 0 0 0 0 0 8 1 1 0 0 0 0 0 0 0 0 7 r7 r7 0 0 0 0 0 0 0 0 6 r6 r6 0 0 0 0 0 0 0 0 5 r5 r5 1 1 0 0 1 1 0 0 4 r4 r4 0 1 0 1 0 1 0 1 3 r3 r3 0 0 0 0 1 1 1 1 2 r2 r2 0 0 0 0 0 0 0 0 1 r1 r1 0 0 0 0 0 0 0 0 0 r0 r0 1 1 1 1 1 1 1 1 Machine Cycle 1 1 1 1 1 1 1 1 1 1 Z C G m -- m 2 - 39 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set AND obj, #i4 obj (logical product of data memory and immediate data) For no post-increment: cur, [HL], [XY], E:[HL], E:[XY] For post-increment: [HL+], [XY+], E:[HL+], E:[XY+] Function obj, A obj ^ i4 (for post-increment) HL HL + 1 or XY XY + 1 Description The logical product of the data memory specified by obj and the immediate data is taken, and the results stored to data memory and the accumulator. For postincremented operations, the HL or XY register is then incremented. Flags Flags affected by execution of this instruction Flag change conditions if obj ^ i4 = 0 then Z 1 else Z 0 (for post-increment) if HL + 1 = 0 or XY + 1 = 0 then G 1 else G 0 Codes/Cycles Z C G m -- m Operand cur, #i4 [HL], #i4 [XY], #i4 E:[HL], #i4 E:[XY], #i4 [HL+], #i4 [XY+], #i4 E:[HL+], #i4 E:[XY+], #i4 Instruction Code 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 i3 0 0 0 0 0 0 0 0 i2 1 1 1 1 1 1 1 1 9 i1 0 0 0 0 0 0 0 0 8 i0 0 0 0 0 1 1 1 1 7 r7 0 0 0 0 0 0 0 0 6 r6 1 1 1 1 1 1 1 1 5 r5 1 1 0 0 1 1 0 0 4 r4 0 1 0 1 0 1 0 1 3 r3 i3 i3 i3 i3 i3 i3 i3 i3 2 r2 i2 i2 i2 i2 i2 i2 i2 i2 1 r1 i1 i1 i1 i1 i1 i1 i1 i1 Machine Cycle 0 r0 i0 i0 i0 i0 i0 i0 i0 i0 1 1 1 1 1 1 1 1 1 2 - 40 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set Bcond radr8 Function if cond is true, then PC Next PC + radr8 else PC PC + 1 (however,-128 radr +127 Next PC indicates the address following this instruction (PC+1)) Instruction description BC or BLT BNC or BGE BLE BGT BNG BZ or BEQ BNZ or BNE Description (conditional branch) Condition C=1 C=0 C=1 C=0 Z=1 Z=0 G=0 Z=1 Z=0 If the condition is true, the content of radr8 is added to Next PC and program execution branches. If the condition is false the content of PC is incremented by one, and the next instruction is executed. The branch destination address is a range of -128 to +127 from the Next PC address. The 8 bits in the instruction code (a7 to a0) correspond to radr8, with the 8th bit (a7) used as a sign. It indicates the relative displacement from the address immediately after the instruction. Branches across program memory space page boundaries are possible. In Assembler it is possible to directly specify an address within the branch range (label) instead of radr8. Flags Flags affected by execution of this instruction Z C G -- Codes/Cycles Operand BC or BLT BNC or BGE BZ or BEQ BNZ or BNE BLE BGT BNG Instruction Code 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 1 1 1 1 0 9 1 1 0 0 1 1 0 8 a7 a7 a7 a7 a7 a7 a7 7 0 1 0 1 0 1 0 6 a6 a6 a6 a6 a6 a6 a6 5 a5 a5 a5 a5 a5 a5 a5 4 a4 a4 a4 a4 a4 a4 a4 3 a3 a3 a3 a3 a3 a3 a3 2 a2 a2 a2 a2 a2 a2 a2 1 a1 a1 a1 a1 a1 a1 a1 -- -- Machine Cycle 1 1 1 1 1 1 1 0 a0 a0 a0 a0 a0 a0 a0 2 - 41 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set BCLR obj. n obj For no post-increment: cur, [HL], [XY], E:[HL], E:[XY] For post-increment: [HL+], [XY+], E:[HL+], E:[XY+] Function obj. n 0, A obj (n = 0 ~ 3) (for post-increment) HL HL + 1 or XY XY + 1 Description (data memory bit clear) n bits of the data memory specified by obj are cleared. After the clear operation, the content of obj is stored to the accumulator. The value of n is 0 to 3, indicating the positions of the bits to be cleared. For post-incremented operations, the HL or XY register is then incremented. Flags Flags affected by execution of this instruction Flag change conditions if obj. n 0 then obj = 0 then Z 1 else Z 0 (for post-increment) if HL + 1 = 0 or XY + 1 = 0 then G 1 else G 0 Codes/Cycles Operand cur, A [HL], A [XY], A E:[HL], A E:[XY], A [HL+], A [XY+], A E:[HL+], A E:[XY+], A Instruction Code 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 n3 0 0 0 0 0 0 0 0 n2 1 1 1 1 1 1 1 1 9 n1 0 0 0 0 0 0 0 0 8 n0 0 0 0 0 1 1 1 1 7 r7 0 0 0 0 0 0 0 0 6 r6 1 1 1 1 1 1 1 1 5 r5 1 1 0 0 1 1 0 0 4 r4 0 1 0 1 0 1 0 1 3 r3 n3 n3 n3 n3 n3 n3 n3 n3 2 r2 n2 n2 n2 n2 n2 n2 n2 n2 1 r1 n1 n1 n1 n1 n1 n1 n1 n1 0 r0 n0 n0 n0 n0 n0 n0 n0 n0 Machine Cycle 1 1 1 1 1 1 1 1 1 Z C G m -- m [Note] The relation between n(0-3) in the operand and n3-n0 in the instruction code is shown below. Operand value for n n3-n0 values in instruction code 0 0EH 1 0DH 2 0BH 3 7H 2 - 42 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set BMOV obj. n, A. n obj [HL], [XY], E:[HL], E:[XY] Function obj.n A.n, A obj (n = 0 ~ 3) Description (transfer bit to data memory) n bits of the accumulator are transferred to bit n of the data memory specified by obj. After the operation, the content of data memory is stored to the accumulator. The value of n is 0 to 3, indicating the positions of the bits to be cleared. Flags Flags affected by execution of this instruction Flag change conditions if obj.n A.n then obj = 0 then Z 1 else Z 0 Codes/Cycles Operand [HL]. n, A. n [XY]. n, A. n E:[HL]. n, A. n E:[XY]. n, A. n Instruction Code 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 n1 n1 n1 n1 9 n0 n0 n0 n0 8 0 0 0 0 7 1 1 1 1 6 1 1 1 1 5 1 1 0 0 4 0 1 0 1 3 n3 n3 n3 n3 2 n2 n2 n2 n2 1 n1 n1 n1 n1 0 n0 n0 n0 n0 Machine Cycle 1 1 1 1 Z C G m -- -- [Note] The value n used to specify the accumulator bits is represented by n1 and n0 in bits 10 and 9 of the instruction code, as shown below. Operand value for n n1, n0 values in instruction code 0 0H 1 1H 2 2H 3 3H The relation between the data memory bit specification n and n3-n0 in the instruction code is shown below. Data memory value for n n3-n0 values in instruction code 0 1H 1 2H 2 4H 3 8H [Note] Only the nX-4/300 core has BMOV instruction. 2 - 43 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set BNOT obj. n obj For no post-increment: cur, [HL], [XY], E:[HL], E:[XY] For post-increment: [HL+], [XY+], E:[HL+], E:[XY+] Function obj. n obj. n, A obj (n = 0 ~ 3) (for post-increment) HL HL + 1 or XY XY + 1 Description (data memory bit reversal) n bits of the data memory specified by obj are reversed. After the operation, the content of obj is stored to the accumulator. The value of n is 0 to 3, indicating the positions of the bits to be reversed. For post-incremented operations, the HL or XY register is then incremented. Flags Flags affected by execution of this instruction Flag change conditions if obj. n obj. n then obj = 0 then Z 1 else Z 0 (for post-increment) if HL + 1 = 0 or XY + 1 = 0 then G 1 else G 0 Codes/Cycles Operand cur, A [HL], A [XY], A E:[HL], A E:[XY], A [HL+], A [XY+], A E:[HL+], A E:[XY+], A Instruction Code 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 n3 0 0 0 0 0 0 0 0 n2 0 0 0 0 0 0 0 0 9 n1 0 0 0 0 0 0 0 0 8 n0 0 0 0 0 1 1 1 1 7 r7 0 0 0 0 0 0 0 0 6 r6 1 1 1 1 1 1 1 1 5 r5 1 1 0 0 1 1 0 0 4 r4 0 1 0 1 0 1 0 1 3 r3 n3 n3 n3 n3 n3 n3 n3 n3 2 r2 n2 n2 n2 n2 n2 n2 n2 n2 1 r1 n1 n1 n1 n1 n1 n1 n1 n1 0 r0 n0 n0 n0 n0 n0 n0 n0 n0 Machine Cycle 1 1 1 1 1 1 1 1 1 Z C G m -- m [Note] The relation between n(0-3) in the operand and n3-n0 in the instruction code is shown below. Operand value for n n3-n0 values in instruction code 0 1H 1 2H 2 4H 3 8H 2 - 44 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set BSET obj. n obj For no post-increment: cur, [HL], [XY], E:[HL], E:[XY] For post-increment: [HL+], [XY+], E:[HL+], E:[XY+] Function obj. n 1, A obj (n = 0 ~ 3) (for post-increment) HL HL + 1 or XY XY + 1 Description (data memory bit set) n bits of the data memory specified by obj are set. After the operation, the content of obj is stored to the accumulator. The value of n is 0 to 3, indicating the positions of the bits to be set. For post-incremented operations, the HL or XY register is then incremented. Flags Flags affected by execution of this instruction Flag change conditions (for post-increment) if HL + 1 = 0 or XY + 1 = 0 then G 1 else G 0 Codes/Cycles Operand cur. n [HL]. n [XY]. n E:[HL]. n E:[XY]. n [HL+]. n [XY+]. n E:[HL+]. n E:[XY+]. n Instruction Code 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 n3 0 0 0 0 0 0 0 0 n2 0 0 0 0 0 0 0 0 9 n1 1 1 1 1 1 1 1 1 8 n0 0 0 0 0 1 1 1 1 7 r7 0 0 0 0 0 0 0 0 6 r6 1 1 1 1 1 1 1 1 5 r5 1 1 0 0 1 1 0 0 4 r4 0 1 0 1 0 1 0 1 3 r3 n3 n3 n3 n3 n3 n3 n3 n3 2 r2 n2 n2 n2 n2 n2 n2 n2 n2 1 r1 n1 n1 n1 n1 n1 n1 n1 n1 0 r0 n0 n0 n0 n0 n0 n0 n0 n0 Machine Cycle 1 1 1 1 1 1 1 1 1 Z C G -- -- m [Note] The relation between n(0-3) in the operand and n3-n0 in the instruction code is shown below. Operand value for n n3-n0 values in instruction code 0 1H 1 2H 2 4H 3 8H 2 - 45 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set BTST obj. n obj For no post-increment: cur, [HL], [XY], E:[HL], E:[XY] For post-increment: [HL+], [XY+], E:[HL+], E:[XY+] Function Z obj. n, (n = 0 ~ 3) (for post-increment) HL HL + 1 or XY XY + 1 Description (data memory bit test) n bits of the data memory specified by obj are tested, and if one then Z 0, and if 0 then Z 1. The value of n is 0 to 3, indicating the positions of the bits to be tested. For post-incremented operations, the HL or XY register is then incremented. Flags Flags affected by execution of this instruction See function column (for post-increment) if HL + 1 = 0 or XY + 1 = 0 then G 1 else G 0 Codes/Cycles Operand cur, A [HL], A [XY], A E:[HL], A E:[XY], A [HL+], A [XY+], A E:[HL+], A E:[XY+], A Instruction Code 15 14 13 12 11 10 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 n3 0 0 0 0 0 0 0 0 n2 1 1 1 1 1 1 1 1 9 n1 0 0 0 0 0 0 0 0 8 n0 0 0 0 0 1 1 1 1 7 r7 1 1 1 1 1 1 1 1 6 r6 0 0 0 0 0 0 0 0 5 r5 1 1 0 0 1 1 0 0 4 r4 0 1 0 1 0 1 0 1 3 r3 n3 n3 n3 n3 n3 n3 n3 n3 2 r2 n2 n2 n2 n2 n2 n2 n2 n2 1 r1 n1 n1 n1 n1 n1 n1 n1 n1 0 r0 n0 n0 n0 n0 n0 n0 n0 n0 Machine Cycle 1 1 1 1 1 1 1 1 1 Z C G m -- m [Note] The relation between n(0-3) in the operand and n3-n0 in the instruction code is shown below. Operand value for n n3-n0 values in instruction code 0 1H 1 2H 2 4H 3 8H 2 - 46 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set CAL cadr12 obj (SP) PC, PC11~0 cadr12, SP SP + 1 Description (subroutine call) The contents of the program counter (PC) are saved to the call stack, and the subroutine called. The call stack pointer is then incremented. The subroutine address is a 12-bit immediate value specifying an absolute address in the program memory space page (4K word). In other words, the content does not change between the 15bit PC value and the 12-bit specification. cadr12 specifies the called address. Flags Flags affected by execution of this instruction Z C G -- Codes/Cycles Operand cadr12 Instruction Code 15 14 13 12 11 10 1 1 1 1 9 8 a8 7 a7 6 a6 5 a5 4 a4 3 a3 2 a2 1 a1 -- -- 0 a0 Machine Cycle 1 a11 a10 a9 2 - 47 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set CMP obj, A obj (comparison of data memory and accumulator) For no post-increment: sfr, cur, [HL], [XY], E:[HL], E:[XY] For post-increment: [HL+], [XY+], E:[HL+], E:[XY+] Function obj - A if obj = A then Z 1, C 0 if obj > A then Z 0, C 0 if obj < A then Z 0, C 1 (for post-increment) HL HL + 1 or XY XY + 1 Description The content of the data memory specified by obj are compared to the contents of the accumulator, and the results reflected in a flag. For post-incremented operations, the HL or XY register is then incremented. Flags Flags affected by execution of this instruction Refer to function column (for post-increment) if HL + 1 = 0 or XY + 1 = 0 then G 1 else G 0 Codes/Cycles Operand sfr, A cur, A [HL], A [XY], A E:[HL], A E:[XY], A [HL+], A [XY+], A E:[HL+], A E:[XY+], A Instruction Code 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 9 1 1 0 0 0 0 0 0 0 0 8 0 0 0 0 0 0 0 0 0 0 7 r7 r7 0 0 0 0 0 0 0 0 6 r6 r6 0 0 0 0 0 0 0 0 5 r5 r5 1 1 0 0 1 1 0 0 4 r4 r4 0 1 0 1 0 1 0 1 3 r3 r3 0 0 0 0 1 1 1 1 2 r2 r2 1 1 1 1 1 1 1 1 1 r1 r1 0 0 0 0 0 0 0 0 0 r0 r0 0 0 0 0 0 0 0 0 Machine Cycle 1 1 1 1 1 1 1 1 1 1 Z C G m m m 2 - 48 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set CMP obj, #i4 obj (comparison of data memory and immediate data) For no post-increment: cur, [HL], [XY], E:[HL], E:[XY] For post-increment: [HL+], [XY+], E:[HL+], E:[XY+] Function obj - i4 if obj = i4 then Z 1, C 0 if obj > i4 then Z 0, C 0 if obj < i4 then Z 0, C 1 (for post-increment) HL HL + 1 or XY XY + 1 Description The contents of the data memory specified by obj are compared to the immediate data, and the results reflected in a flag. For post-incremented operations, the HL or XY register is then incremented. Flags Flags affected by execution of this instruction Refer to function column (for post-increment) if HL + 1 = 0 or XY + 1 = 0 then G 1 else G 0 Codes/Cycles Operand cur, #i4 [HL], #i4 [XY], #i4 E:[HL], #i4 E:[XY], #i4 [HL+], #i4 [XY+], #i4 E:[HL+], #i4 E:[XY+], #i4 Instruction Code 15 14 13 12 11 10 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i3 0 0 0 0 0 0 0 0 i2 1 1 1 1 1 1 1 1 9 i1 1 1 1 1 1 1 1 1 8 i0 0 0 0 0 1 1 1 1 7 r7 1 1 1 1 1 1 1 1 6 r6 0 0 0 0 0 0 0 0 5 r5 1 1 0 0 1 1 0 0 4 r4 0 1 0 1 0 1 0 1 3 r3 i3 i3 i3 i3 i3 i3 i3 i3 2 r2 i2 i2 i2 i2 i2 i2 i2 i2 1 r1 i1 i1 i1 i1 i1 i1 i1 i1 0 r0 i0 i0 i0 i0 i0 i0 i0 i0 Machine Cycle 1 1 1 1 1 1 1 1 1 Z C G m m m 2 - 49 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set DEC obj obj For no post-increment: sfr, cur, [HL], [XY], E:[HL], E:[XY] For post-increment: [HL+], [XY+], E:[HL+], E:[XY+] Function obj, A obj - 1 (for post-increment) HL HL + 1 or XY XY + 1 Description (decrement) The content of the data memory specified by obj is decremented and the results stored to the accumulator. For post-incremented operations, the HL or XY register is then incremented. Flags Flags affected by execution of this instruction Flag change conditions if obj - 1 = 0FH then C 1 else C 0 if obj - 1 = 0 then Z 1 else Z 0 (for post-increment) if HL + 1 = 0 or XY + 1 then G 1 else G 0 Codes/Cycles Operand sfr cur [HL] [XY] E:[HL] E:[XY] [HL+] [XY+] E:[HL+] E:[XY+] Instruction Code 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 9 0 0 0 0 0 0 0 0 0 0 8 1 1 1 1 1 1 1 1 1 1 7 r7 r7 0 0 0 0 0 0 0 0 6 r6 r6 0 0 0 0 0 0 0 0 5 r5 r5 1 1 0 0 1 1 0 0 4 r4 r4 0 1 0 1 0 1 0 1 3 r3 r3 0 0 0 0 1 1 1 1 2 r2 r2 0 0 0 0 0 0 0 0 1 r1 r1 0 0 0 0 0 0 0 0 0 r0 r0 1 1 1 1 1 1 1 1 Machine Cycle 1 1 1 1 1 1 1 1 1 1 Z C G m m m 2 - 50 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set DI Function MIE 0 Description Clears the master interrupt enable flag. Flags Flags affected by execution of this instruction Z (MIE flag clear) C G -- Codes/Cycles Operand DI Instruction Code 15 14 13 12 11 10 0 0 0 0 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 1 2 1 1 1 -- -- 0 1 Machine Cycle 1 EI Function MIE 1 Description Sets the master interrupt enable flag. Flags Flags affected by execution of this instruction Z (MIE flag set) C G -- Codes/Cycles Operand EI Instruction Code 15 14 13 12 11 10 0 0 0 0 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 1 2 1 1 1 -- -- 0 0 Machine Cycle 1 2 - 51 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set FCLR C Function C0 Description Clears the carry flag. Flags Flags affected by execution of this instruction Z (carry flag clear) C G -- Codes/Cycles Operand C Instruction Code 15 14 13 12 11 10 0 0 0 0 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 1 m -- 0 1 Machine Cycle 1 FCLR FLAG Function Z 0, C 0, G 0 Description Clears the zero flag, carry flag and G flag. Flags Flags affected by execution of this instruction (zero flag, csrry flag and G flag clear) Z C G m Codes/Cycles Operand FLAG Instruction Code 15 14 13 12 11 10 0 0 0 0 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 1 1 0 m m 0 1 Machine Cycle 1 [Note] Only the nX-4/300 core has FCLR FLAG instruction. 2 - 52 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set FCLR G Function G0 Description Clears the G flag. Flags Flags affected by execution of this instruction Z (G flag clear) C G -- Codes/Cycles Operand G Instruction Code 15 14 13 12 11 10 0 0 0 0 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 1 -- m 0 0 Machine Cycle 1 FCLR Z Function Z0 Description Clears the zero flag. Flags Flags affected by execution of this instruction Z (zero flag clear) C G m Codes/Cycles Operand Z Instruction Code 15 14 13 12 11 10 0 0 0 0 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 1 1 0 -- -- 0 0 Machine Cycle 1 2 - 53 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set FSET C Function C1 Description Sets the carry flag. Flags Flags affected by execution of this instruction Z (set carry flag) C G -- Codes/Cycles Operand C Instruction Code 15 14 13 12 11 10 0 0 0 0 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 1 1 1 m -- 0 1 Machine Cycle 1 FSET FLAG Function Z 1, C 1, G 1 Description Sets the zero flag, carry flag and G flag. Flags Flags affected by execution of this instruction (zero flag, carry flag and G flag set) Z C G m Codes/Cycles Operand FLAG Instruction Code 15 14 13 12 11 10 0 0 0 0 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 1 2 0 1 0 m m 0 1 Machine Cycle 1 [Note] Only the nX-4/300 core has FSET FLAG instruction. 2 - 54 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set FSET G Function G1 Description Sets the G flag. Flags Flags affected by execution of this instruction Z C (set G flag) G -- Codes/Cycles Operand G Instruction Code 15 14 13 12 11 10 0 0 0 0 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 1 1 1 -- m 0 0 Machine Cycle 1 FSET Z Function Z1 Description Sets the zero flag. Flags Flags affected by execution of this instruction Z (set zero flag) C G m Codes/Cycles Operand Z Instruction Code 15 14 13 12 11 10 0 0 0 0 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 1 2 0 1 0 -- -- 0 0 Machine Cycle 1 2 - 55 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set HALT Function Halt CPU Description (CPU halt mode) Switches the CPU to the halt mode. [Precautions] Always use an NOP instruction immediately after the HALT instruction. Example * * * HALT NOP * * * Codes/Cycles Operand HALT Instruction Code 15 14 13 12 11 10 0 0 0 0 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 1 Machine Cycle 1 2 - 56 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set INC obj obj For no post-increment: sfr, cur, [HL], [XY], E:[HL], E:[XY] For post-increment: [HL+], [XY+], E:[HL+], E:[XY+] Function obj, A obj + 1 (for post-increment) HL HL + 1 or XY XY + 1 Description (increment) The content of the data memory specified by obj is incremented, and the results stored to the accumulator. For post-incremented operations, the HL or XY register is then incremented. Flags Flags affected by execution of this instruction Flag change conditions if obj + 1 = 0 then C 1, Z 1 else C 0, Z 0 (for post-increment) if HL + 1 = 0 or XY + 1 = 0 then G 1 else G 0 Codes/Cycles Operand sfr cur [HL] [XY] E:[HL] E:[XY] [HL+] [XY+] E:[HL+] E:[XY+] Instruction Code 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 9 0 0 0 0 0 0 0 0 0 0 8 0 0 1 1 1 1 1 1 1 1 7 r7 r7 0 0 0 0 0 0 0 0 6 r6 r6 0 0 0 0 0 0 0 0 5 r5 r5 1 1 0 0 1 1 0 0 4 r4 r4 0 1 0 1 0 1 0 1 3 r3 r3 0 0 0 0 1 1 1 1 2 r2 r2 0 0 0 0 0 0 0 0 1 r1 r1 0 0 0 0 0 0 0 0 Machine Cycle 0 r0 r0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 Z C G m m m 2 - 57 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set INCB obj obj HL, XY Function obj obj + 1 (byte increment) Description Increments the HL or XY registers in byte units. Flags Flags affected by execution of this instruction Flag change conditions if HL + 1 = 0 or XY + 1 = 0 then G 1 else G 0 Codes/Cycles Operand HL XY Instruction Code 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 0 0 9 0 0 8 0 0 7 0 0 6 0 0 5 0 0 (HL, XY pair register increment) Z C G -- -- m 4 1 1 3 1 1 2 0 0 1 0 0 0 0 1 Machine Cycle 1 1 INCW RA obj RA RA + 1 (word increment) Description Increments the RA register in word units. Flags Flags affected by execution of this instruction Flag change conditions if RA + 1 = 0 then G 1 else G 0 Codes/Cycles Operand RA Instruction Code 15 14 13 12 11 10 0 0 0 0 0 0 9 0 8 0 7 0 6 0 5 0 4 1 3 1 (RA register increment) Z C G -- -- m 2 0 1 1 0 0 Machine Cycle 1 2 - 58 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set JMP cadr12 Function PC11~0 cadr12 Description (branch) 12-bit immediate data is used to specify the program memory space page region (4K word), and branch to an absolute address. There is no change in data from 15-bit PC to 12-bit. cadr12 specifies the called address. Flags Flags affected by execution of this instruction Z C G -- Codes/Cycles Operand cadr12 Instruction Code 15 14 13 12 11 10 1 1 1 0 9 8 a8 7 a7 6 a6 5 a5 4 a4 3 a3 2 a2 1 a1 -- -- 0 a0 Machine Cycle 1 a11 a10 a9 JMP PC+A Function PC PC +A+ 1 Description (branch as per content of accumulator) The content of the accumulator is added to the program counter (PC), one added, and the result stored to the PC. Branches are possible across program memory space page boundaries. Flags Flags affected by execution of this instruction Z C G -- Codes/Cycles Operand PC+A Instruction Code 15 14 13 12 11 10 0 0 0 0 0 0 9 0 8 0 7 0 6 0 5 0 4 1 3 0 2 1 1 1 -- -- Machine Cycle 0 1 1 2 - 59 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set LCAL cadr16 Function (SP) PC, PC cadr16, SP SP + 1 Description (call subroutine) The contents of the second word of the program counter (PC) are saved to the call stack, and the subroutine called. The call stack pointer is then incremented. The subroutine address is a 16-bit immediate value specifying an absolute address in the program memory space (64K word). cadr16 specifies the called address. Flags Flags affected by execution of this instruction Z C G -- Codes/Cycles Operand cadr16 Instruction Code 15 14 13 12 11 10 0 0 0 0 0 0 9 0 8 0 a8 7 0 a7 6 0 a6 5 0 a5 4 1 a4 3 0 a3 2 1 a2 1 0 a1 -- -- Machine Cycle 2 0 1 a0 a15 a14 a13 a12 a11 a10 a9 LJMP cadr16 Function PC cadr16 Description (branch) 16-bit immediate data specifies an absolute address in the program memory space (64K word), and the program branches to that address. cadr16 specifies the called address. Flags Flags affected by execution of this instruction Z C G -- Codes/Cycles Operand cadr16 Instruction Code 15 14 13 12 11 10 0 0 0 0 0 0 9 0 8 0 a8 7 0 a7 6 0 a6 5 0 a5 4 1 a4 3 0 a3 2 1 a2 1 0 a1 -- -- Machine Cycle 2 0 0 a0 a15 a14 a13 a12 a11 a10 a9 2 - 60 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set MCLR obj, #m obj For no post-increment: cur, [HL], [XY], E:[HL], E:[XY] For post-increment: [HL+], [XY+], E:[HL+], E:[XY+] Function Bits not masked by obj #m 0, A obj (m = 0 ~ 0FH) (for post-increment) HL HL + 1 or XY XY + 1 Description (data memory bit clear) Clears all bits not masked by immediate data m, in the data memory specified by obj. After the clear operation the content of obj is stored to the accumulator. m is a value in the range 0 to 0FH, with a "1" masking a bit and a "0" marking a bit to be cleared. For post-increment operations, the HL or XY register is incremented after execution. Flags Flags affected by execution of this instruction Flag change conditions if obj = 0 then Z 1 else Z 0 (for post-increment) if HL + 1 = 0 or XY + 1 = 0 then G 1 else G 0 Codes/Cycles Operand cur. #m [HL]. #m [XY]. #m E:[HL]. #m E:[XY]. #m [HL+]. #m [XY+]. #m E:[HL+]. #m E:[XY+]. #m Instruction Code 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 9 0 0 0 0 0 0 0 0 8 0 0 0 0 1 1 1 1 7 0 0 0 0 0 0 0 0 6 r6 1 1 1 1 1 1 1 1 5 r5 1 1 0 0 1 1 0 0 4 r4 0 1 0 1 0 1 0 1 3 r3 2 r2 1 r1 0 r0 m3 m2 m1 m0 r7 Machine Cycle 1 1 1 1 1 1 1 1 1 Z C G m -- m m3 m2 m1 m0 m3 m2 m1 m0 m3 m2 m1 m0 m3 m2 m1 m0 m3 m2 m1 m0 m3 m2 m1 m0 m3 m2 m1 m0 m3 m2 m1 m0 2 - 61 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set MMOV obj, #m, A.n obj [HL], [XY], E:[HL], E:[XY] Function (bit transfer to data memory) Bits not masked by obj #m A. n, A obj (m = 0 ~ 0FH, n = 0 ~ 3) Description Transfers bits specified by n from accumulator to bits of the data memory specified by obj which are not masked by m. After the transfer, the data memory is stored to the accumulator. m is a value from 0 to 0FH, which a "0" masking a bit and a "1" masking a bit for transfer. n is a value 0 to 3, and marks the accumulator bit position. Example 3 A 0 2 1 1 0 0 0 Data memory 3 1 2 1 1 1 0 1 Execute MMOV obj, #1001B, A.0 3 A 0 2 1 1 1 0 0 Data memory 3 0 2 1 1 1 0 0 Bit not masked Bit masked Bit not masked Flags Flags affected by execution of this instruction Flag change conditions if obj = 0 then Z 1 else Z 0 Codes/Cycles Operand [HL], #m, A. n [XY], #m, A. n E:[HL], #m, A. n E:[XY], #m, A. n Instruction Code 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 n1 n1 n1 n1 9 n0 n0 n0 n0 8 0 0 0 0 7 1 1 1 1 6 1 1 1 1 5 1 1 0 0 4 0 1 0 1 3 2 1 Machine Cycle 0 1 1 1 1 Z C G m -- -- m3 m2 m1 m0 m3 m2 m1 m0 m3 m2 m1 m0 m3 m2 m1 m0 [Note] Only the nX-4/300 core has MMOV instruction. 2 - 62 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set MNOT obj, #m obj For no post-increment: cur, [HL], [XY], E:[HL], E:[XY] For post-increment: [HL+], [XY+], E:[HL+], E:[XY+] Function Reverses bits not masked by obj #m A obj (m = 0 ~ 0FH) (for post-increment) HL HL + 1 or XY XY + 1 Description (data memory bit reversal) Reverses all bits not masked by m in the data memory specified by obj. After the clear operation the content of obj is stored to the accumulator. m is a value in the range 0 to 0FH, with a "0" masking a bit and a "1" marking a bit to be reversed. For post-increment operations, the HL or XY register is incremented after execution. Flags Flags affected by execution of this instruction Flag change conditions if obj = 0 then Z 1 else Z 0 (for post-increment) if HL + 1 = 0 or XY + 1 = 0 then G 1 else G 0 Codes/Cycles Operand cur. #m [HL]. #m [XY]. #m E:[HL]. #m E:[XY]. #m [HL+]. #m [XY+]. #m E:[HL+]. #m E:[XY+]. #m Instruction Code 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 0 0 0 0 0 0 0 0 8 0 0 0 0 1 1 1 1 7 0 0 0 0 0 0 0 0 6 r6 1 1 1 1 1 1 1 1 5 r5 1 1 0 0 1 1 0 0 4 r4 0 1 0 1 0 1 0 1 3 r3 2 r2 1 r1 0 r0 m3 m2 m1 m0 r7 Machine Cycle 1 1 1 1 1 1 1 1 1 Z C G m -- m m3 m2 m1 m0 m3 m2 m1 m0 m3 m2 m1 m0 m3 m2 m1 m0 m3 m2 m1 m0 m3 m2 m1 m0 m3 m2 m1 m0 m3 m2 m1 m0 2 - 63 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set MOV A, obj obj (transfer data memory content to accumulator) For no post-increment: direct, [HL], [XY], E:[HL], E:[XY] For post-increment: [HL+], [XY+], E:[HL+], E:[XY+] Function A obj (for post-increment) HL HL + 1 or XY XY + 1 Description Transfers content of data memory specified by obj to the accumulator. For postincrement operations, the HL or XY register is incremented after execution. Flags Flags affected by execution of this instruction Flag change conditions if A = 0 then Z 1 else Z 0 (for post-increment) if HL + 1 = 0 or XY + 1 = 0 then G 1 else G 0 Codes/Cycles Operand A, direct A, [HL] A, [XY] A, E:[HL] A, E:[XY] A, [HL+] A, [XY+] A, E:[HL+] A, E:[XY+] Instruction Code 15 14 13 12 11 10 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 1 1 1 1 1 1 1 1 8 r8 1 1 1 1 1 1 1 1 7 r7 0 0 0 0 0 0 0 0 6 r6 0 0 0 0 0 0 0 0 5 r5 1 1 0 0 1 1 0 0 4 r4 0 1 0 1 0 1 0 1 3 r3 0 0 0 0 1 1 1 1 2 r2 0 0 0 0 0 0 0 0 1 r1 0 0 0 0 0 0 0 0 0 r0 0 0 0 0 0 0 0 0 r11 r10 r9 Machine Cycle 1 1 1 1 1 1 1 1 1 Z C G m -- m 2 - 64 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set MOV A #i4 obj A i4 Description (transfer immediate data to accumulator) Transfers immediate data i4 to the accumulator. Flags Flags affected by execution of this instruction Flag change conditions if A = 0 then Z 1 else Z 0 Codes/Cycles Operand A, #i4 Instruction Code 15 14 13 12 11 10 0 0 0 0 0 0 9 0 8 1 7 1 6 1 5 0 4 0 3 i3 2 i2 1 i1 0 i0 Machine Cycle 1 Z C G m -- -- 2 - 65 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set MOV obj, A obj (transfer accumulator to data memory) For no post-increment: direct, [HL], [XY], E:[HL], E:[XY] For post-increment: [HL+], [XY+], E:[HL+], E:[XY+] Function obj A (for post-increment) HL HL + 1 or XY XY + 1 Description Transfers content of accumulator to data memory specified by obj. For post-increment operations, the HL or XY register is incremented after execution. Flags Flags affected by execution of this instruction Flag change conditions (for post-increment) if HL + 1 = 0 or XY + 1 = 0 then G 1 else G 0 Codes/Cycles Operand direct, A [HL], A [XY], A E:[HL], A E:[XY], A [HL+], A [XY+], A E:[HL+], A E:[XY+], A Instruction Code 15 14 13 12 11 10 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 9 0 0 0 0 0 0 0 0 8 r8 0 0 0 0 0 0 0 0 7 r7 0 0 0 0 0 0 0 0 6 r6 0 0 0 0 0 0 0 0 5 r5 1 1 0 0 1 1 0 0 4 r4 0 1 0 1 0 1 0 1 3 r3 0 0 0 0 1 1 1 1 2 r2 0 0 0 0 0 0 0 0 1 r1 0 0 0 0 0 0 0 0 0 r0 0 0 0 0 0 0 0 0 r11 r10 r9 Machine Cycle 1 1 1 1 1 1 1 1 1 Z C G -- -- m 2 - 66 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set MOV obj, #i4 obj (transfer immediate data to accumulator and data memory) For no post-increment: cur, [HL], [XY], E:[HL], E:[XY] For post-increment: [HL+], [XY+], E:[HL+], E:[XY+] Function obj, A i4 (for post-increment) HL HL + 1 or XY XY + 1 Description Transfers immediate data i4 to accumulator and data memory specified by obj. For post-increment operations, the HL or XY register is incremented after execution. Flags Flags affected by execution of this instruction Flag change conditions if A = 0 then Z 1 else Z 0 (for post-increment) if HL + 1 = 0 or XY + 1 = 0 then G 1 else G 0 Codes/Cycles Operand cur, #i4 [HL], #i4 [XY], #i4 E:[HL], #i4 E:[XY], #i4 [HL+], #i4 [XY+], #i4 E:[HL+], #i4 E:[XY+], #i4 Instruction Code 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i3 0 0 0 0 0 0 0 0 i2 1 1 1 1 1 1 1 1 9 i1 1 1 1 1 1 1 1 1 8 i0 0 0 0 0 1 1 1 1 7 r7 0 0 0 0 0 0 0 0 6 r6 1 1 1 1 1 1 1 1 5 r5 1 1 0 0 1 1 0 0 4 r4 0 1 0 1 0 1 0 1 3 r3 i3 i3 i3 i3 i3 i3 i3 i3 2 r2 i2 i2 i2 i2 i2 i2 i2 i2 1 r1 i1 i1 i1 i1 i1 i1 i1 i1 0 r0 i0 i0 i0 i0 i0 i0 i0 i0 Machine Cycle 1 1 1 1 1 1 1 1 1 Z C G m -- m 2 - 67 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set MOV obj, #i4 obj CBR, EBR, RA0, RA1, RA2, RA3, H, L, X, Y Function obj i4 Description (transfer immediate data to registers) Transfer immediate data i4 to the register specified by obj. Flags Flags affected by execution of this instruction Z C G -- Codes/Cycles Operand CBR, #i4 EBR, #i4 RA0, #i4 RA1, #i4 RA2, #i4 RA3, #i4 H, #i4 L, #i4 X, #i4 Y, #i4 Instruction Code 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 0 0 1 1 1 1 0 0 0 0 8 0 0 0 0 0 0 1 1 1 1 7 0 0 0 0 0 0 0 0 0 0 6 0 0 0 0 0 0 0 0 0 0 5 1 1 0 0 1 1 1 1 0 0 4 1 0 0 1 0 1 1 0 1 0 3 i3 i3 i3 i3 i3 i3 i3 i3 i3 i3 2 i2 i2 i2 i2 i2 i2 i2 i2 i2 i2 1 i1 i1 i1 i1 i1 i1 i1 i1 i1 i1 -- -- Machine Cycle 0 i0 i0 i0 i0 i0 i0 i0 i0 i0 i0 1 1 1 1 1 1 1 1 1 1 2 - 68 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set MOVHB obj, [RA] obj For no post-increment: [HL], [XY], E:[HL], E:[XY] For post-increment: [HL+], [XY+], E:[HL+], E:[XY+] Function obj (RA) 11~8 obj + 1 (RA) 15~12 (for post-increment) HL HL + 2 or XY XY + 2 Description (ROM table reference) This instruction refers to the ROM table. RA3 through RA0 compose the address as indicated below. The high 8-bit data at that address in program memory is transferred to the data memory specified by obj. RA3 RA2 8 7 RA1 6 5 4 3 RA0 2 1 0 ROM address 15 14 13 12 11 10 9 Invalid for nX-4/250 core Bits 11 through 8 of program memory are transferred to the data memory specified by obj, and bits 15 to 12 to the data memory specified as obj+1. For post-increment operations, the HL or XY register is incremented by 2 after execution. Flags Flags affected by execution of this instruction Flag change conditions (for post-increment) if HL + 2 > 0FFH or XY + 2 > 0FFH then G 1 else G 0 Codes/Cycles Instruction Code 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 1 1 1 1 1 1 1 1 8 1 1 1 1 1 1 1 1 7 0 0 0 0 0 0 0 0 6 0 0 0 0 0 0 0 0 5 1 1 0 0 1 1 0 0 4 0 1 0 1 0 1 0 1 3 0 0 0 0 1 1 1 1 2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 Machine Cycle 2 2 2 2 2 2 2 2 Z C G -- -- m Operand [HL], [RA] [XY], [RA] E:[HL], [RA] E:[XY], [RA] [HL+], [RA] [XY+], [RA] E:[HL+], [RA] E:[XY+], [RA] 2 - 69 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set MOVHB obj, cadr16 obj For no post-increment: [HL], [XY], E:[HL], E:[XY] For post-increment: [HL+], [XY+], E:[HL+], E:[XY+] Function obj (cadr16) 11~8 obj + 1 (cadr16) 15~12 (for post-increment) HL HL + 2 or XY XY + 2 Description (ROM table reference) This instruction refers to the ROM table. The high 8-bit data in program memory specified by cadr16 is byte-transferred to the data memory specified by obj. Bits 11 through 8 of program memory are transferred to the data memory specified by obj, and bits 15 to 12 to the data memory specified as obj+1. For post-increment operations, the HL or XY register is incremented by 2 after execution. Flags Flags affected by execution of this instruction Flag change conditions (for post-increment) if HL + 2 > 0FFH or XY + 2 > 0FFH then G 1 else G 0 Codes/Cycles Operand [HL], cadr16 [XY], cadr16 E:[HL], cadr16 E:[XY], cadr16 [HL+], cadr16 [XY+], cadr16 E:[HL+], cadr16 E:[XY+], cadr16 Instruction Code 15 0 a15 0 a15 0 a15 0 a15 0 a15 0 a15 0 a15 0 a15 14 0 a14 0 a14 0 a14 0 a14 0 a14 0 a14 0 a14 0 a14 13 0 a13 0 a13 0 a13 0 a13 0 a13 0 a13 0 a13 0 a13 12 0 a12 0 a12 0 a12 0 a12 0 a12 0 a12 0 a12 0 a12 11 0 a11 0 a11 0 a11 0 a11 0 a11 0 a11 0 a11 0 a11 10 0 a10 0 a10 0 a10 0 a10 0 a10 0 a10 0 a10 0 a10 9 1 a9 1 a9 1 a9 1 a9 1 a9 1 a9 1 a9 1 a9 8 1 a8 1 a8 1 a8 1 a8 1 a8 1 a8 1 a8 1 a8 7 0 a7 0 a7 0 a7 0 a7 0 a7 0 a7 0 a7 0 a7 6 0 a6 0 a6 0 a6 0 a6 0 a6 0 a6 0 a6 0 a6 5 1 a5 1 a5 0 a5 0 a5 1 a5 1 a5 0 a5 0 a5 4 0 a4 1 a4 0 a4 1 a4 0 a4 1 a4 0 a4 1 a4 3 0 a3 0 a3 0 a3 0 a3 1 a3 1 a3 1 a3 1 a3 2 1 a2 1 a2 1 a2 1 a2 1 a2 1 a2 1 a2 1 a2 1 0 a1 0 a1 0 a1 0 a1 0 a1 0 a1 0 a1 0 a1 0 0 a0 0 a0 0 a0 0 a0 0 a0 0 a0 0 a0 0 a0 Machine Cycle 3 3 3 3 3 3 3 3 Z C G -- -- m 2 - 70 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set MOVLB obj, [RA] obj For no post-increment: [HL], [XY], E:[HL], E:[XY] For post-increment: [HL+], [XY+], E:[HL+], E:[XY+] Function obj (RA) 3~0 obj + 1 (RA) 7~4 (for post-increment) HL HL + 2 or XY XY + 2 Description (ROM table reference) This instruction refers to the ROM table. RA3 through RA0 compose the address as indicated below. The low 8-bit data at that address in program memory is transferred to the data memory specified by obj. RA3 RA2 8 7 RA1 6 5 4 3 RA0 2 1 0 ROM address 15 14 13 12 11 10 9 Invalid for nX-4/250 core Bits 3 through 0 of program memory are transferred to the data memory specified by obj, and bits 7 to 4 to the data memory specified as obj+1. For post-increment operations, the HL or XY register is incremented by 2 after execution. Flags Flags affected by execution of this instruction Flag change conditions (for post-increment) if HL + 2 > 0FFH or XY + 2 > 0FFH then G 1 else G 0 Codes/Cycles Instruction Code 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 1 1 1 1 1 1 1 1 8 1 1 1 1 1 1 1 1 7 0 0 0 0 0 0 0 0 6 0 0 0 0 0 0 0 0 5 1 1 0 0 1 1 0 0 4 0 1 0 1 0 1 0 1 3 0 0 0 0 1 1 1 1 2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 Machine Cycle 2 2 2 2 2 2 2 2 Z C G -- -- m Operand [HL], [RA] [XY], [RA] E:[HL], [RA] E:[XY], [RA] [HL+], [RA] [XY+], [RA] E:[HL+], [RA] E:[XY+], [RA] 2 - 71 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set MOVLB obj, cadr16 obj For no post-increment: [HL], [XY], E:[HL], E:[XY] For post-increment: [HL+], [XY+], E:[HL+], E:[XY+] Function obj (cadr16) 3~0 obj + 1 (cadr16 ) 7~4 (for post-increment) HL HL + 2 or XY XY + 2 Description (ROM table reference) This instruction refers to the ROM table. The low 8-bit data in program memory specified by cadr16 is byte-transferred to the data memory specified by obj. Bits 3 through 0 of program memory are transferred to the data memory specified by obj, and bits 7 to 4 to the data memory specified as obj+1. For post-increment operations, the HL or XY register is incremented by 2 after execution. Flags Flags affected by execution of this instruction Flag change conditions (for post-increment) if HL + 2 > 0FFH or XY + 2 > 0FFH then G 1 else G 0 Codes/Cycles Operand [HL], cadr16 [XY], cadr16 E:[HL], cadr16 E:[XY], cadr16 [HL+], cadr16 [XY+], cadr16 E:[HL+], cadr16 E:[XY+], cadr16 Instruction Code 15 0 a15 0 a15 0 a15 0 a15 0 a15 0 a15 0 a15 0 a15 14 0 a14 0 a14 0 a14 0 a14 0 a14 0 a14 0 a14 0 a14 13 0 a13 0 a13 0 a13 0 a13 0 a13 0 a13 0 a13 0 a13 12 0 a12 0 a12 0 a12 0 a12 0 a12 0 a12 0 a12 0 a12 11 0 a11 0 a11 0 a11 0 a11 0 a11 0 a11 0 a11 0 a11 10 0 a10 0 a10 0 a10 0 a10 0 a10 0 a10 0 a10 0 a10 9 1 a9 1 a9 1 a9 1 a9 1 a9 1 a9 1 a9 1 a9 8 1 a8 1 a8 1 a8 1 a8 1 a8 1 a8 1 a8 1 a8 7 0 a7 0 a7 0 a7 0 a7 0 a7 0 a7 0 a7 0 a7 6 0 a6 0 a6 0 a6 0 a6 0 a6 0 a6 0 a6 0 a6 5 1 a5 1 a5 0 a5 0 a5 1 a5 1 a5 0 a5 0 a5 4 0 a4 1 a4 0 a4 1 a4 0 a4 1 a4 0 a4 1 a4 3 0 a3 0 a3 0 a3 0 a3 1 a3 1 a3 1 a3 1 a3 2 1 a2 1 a2 1 a2 1 a2 1 a2 1 a2 1 a2 1 a2 1 0 a1 0 a1 0 a1 0 a1 0 a1 0 a1 0 a1 0 a1 0 1 a0 1 a0 1 a0 1 a0 1 a0 1 a0 1 a0 1 a0 Machine Cycle 3 3 3 3 3 3 3 3 Z C G -- -- m 2 - 72 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set MOVXB obj, [RA] obj (transfer external memory to data memory) For no post-increment: [HL], [XY], E:[HL], E:[XY] For post-increment: [HL+], [XY+], E:[HL+], E:[XY+] Function obj (RA) 3~0 obj + 1 (RA) 7~4 (for post-increment) HL HL + 2 or XY XY + 2 Description This instruction transfers external memory. The address is specified by RA3 to RA0 as indicated below. 8-bit data in external memory specified is byte-transferred to the data memory specified by obj. External memory address RA3 RA2 8 7 RA1 6 5 4 3 RA0 2 1 0 15 14 13 12 11 10 9 Bits 3 through 0 of external memory are transferred to the data memory specified by obj, and bits 7 to 4 to the data memory specified as obj+1. For post-increment operations, the HL or XY register is incremented by 2 after execution. Flags Flags affected by execution of this instruction Flag change conditions (for post-increment) if HL + 2 > 0FFH or XY + 2 > 0FFH then G 1 else G 0 Codes/Cycles Operand [HL], [RA] [XY], [RA] E:[HL], [RA] E:[XY], [RA] [HL+], [RA] [XY+], [RA] E:[HL+], [RA] E:[XY+], [RA] Instruction Code 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 1 1 1 1 1 1 1 1 8 1 1 1 1 1 1 1 1 7 0 0 0 0 0 0 0 0 6 0 0 0 0 0 0 0 0 5 1 1 0 0 1 1 0 0 4 0 1 0 1 0 1 0 1 3 0 0 0 0 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 Machine Cycle 2 2 2 2 2 2 2 2 Z C G -- -- m 2 - 73 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set MOVXB obj, xadr16 obj (transfer external memory to data memory) For no post-increment: [HL], [XY], E:[HL], E:[XY] For post-increment: [HL+], [XY+], E:[HL+], E:[XY+] Function obj (xadr16) 3~0 obj + 1 (xadr16) 7~4 (for post-increment) HL HL + 2 or XY XY + 2 Description This instruction transfers external memory. The address is specified by xadr16. 8-bit data in external memory specified is bytetransferred to the data memory specified by obj. Bits 3 through 0 of external memory are transferred to the data memory specified by obj, and bits 7 to 4 to the data memory specified as obj+1. For post-increment operations, the HL or XY register is incremented by 2 after execution. Flags Flags affected by execution of this instruction Flag change conditions (for post-increment) if HL + 2 > 0FFH or XY + 2 > 0FFH then G 1 else G 0 Codes/Cycles Operand [HL], xadr16 [XY], xadr16 E:[HL], xadr16 E:[XY], xadr16 [HL+], xadr16 [XY+], xadr16 E:[HL+], xadr16 E:[XY+], xadr16 Instruction Code 15 0 a15 0 a15 0 a15 0 a15 0 a15 0 a15 0 a15 0 a15 14 0 a14 0 a14 0 a14 0 a14 0 a14 0 a14 0 a14 0 a14 13 0 a13 0 a13 0 a13 0 a13 0 a13 0 a13 0 a13 0 a13 12 0 a12 0 a12 0 a12 0 a12 0 a12 0 a12 0 a12 0 a12 11 0 a11 0 a11 0 a11 0 a11 0 a11 0 a11 0 a11 0 a11 10 0 a10 0 a10 0 a10 0 a10 0 a10 0 a10 0 a10 0 a10 9 1 a9 1 a9 1 a9 1 a9 1 a9 1 a9 1 a9 1 a9 8 1 a8 1 a8 1 a8 1 a8 1 a8 1 a8 1 a8 1 a8 7 1 a7 1 a7 1 a7 1 a7 1 a7 1 a7 1 a7 1 a7 6 1 a6 1 a6 1 a6 1 a6 1 a6 1 a6 1 a6 1 a6 5 1 a5 1 a5 0 a5 0 a5 1 a5 1 a5 0 a5 0 a5 4 0 a4 1 a4 0 a4 1 a4 0 a4 1 a4 0 a4 1 a4 3 0 a3 0 a3 0 a3 0 a3 1 a3 1 a3 1 a3 1 a3 2 0 a2 0 a2 0 a2 0 a2 0 a2 0 a2 0 a2 0 a2 1 0 a1 0 a1 0 a1 0 a1 0 a1 0 a1 0 a1 0 a1 0 0 a0 0 a0 0 a0 0 a0 0 a0 0 a0 0 a0 0 a0 Machine Cycle 3 3 3 3 3 3 3 3 Z C G -- -- m 2 - 74 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set MOVXB [RA], obj obj (transfer data memory to external memory) For no post-increment: [HL], [XY], E:[HL], E:[XY] For post-increment: [HL+], [XY+], E:[HL+], E:[XY+] Function (RA) 3~0 obj (RA) 7 - 4 obj (for post-increment) HL HL + 2 or XY XY + 2 Description This instruction transfers external memory. The address is specified by RA3 to RA0 as indicated below. Data in the data memory specified by obj is byte-transferred to the specified external memory. External memory address RA3 RA2 8 7 RA1 6 5 4 3 RA0 2 1 0 15 14 13 12 11 10 9 Data memory specified by obj is transferred to bits 3 through 0 of external memory, and data memory specified by obj+1 is transferred to external memory bits 7 to 4. For post-increment operations, the HL or XY register is incremented by 2 after execution. Flags Flags affected by execution of this instruction Flag change conditions (for post-increment) if HL + 2 > 0FFH or XY + 2 > 0FFH then G 1 else G 0 Codes/Cycles Instruction Code 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 1 1 1 1 1 1 1 1 8 1 1 1 1 1 1 1 1 7 0 0 0 0 0 0 0 0 6 0 0 0 0 0 0 0 0 5 1 1 0 0 1 1 0 0 4 0 1 0 1 0 1 0 1 3 0 0 0 0 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 Machine Cycle 3 3 3 3 3 3 3 3 Z C G -- -- m Operand [RA], [HL] [RA], [XY] [RA], E:[HL] [RA], E:[XY] [RA], [HL+] [RA], [XY+] [RA], E:[HL+] [RA], E:[XY+] 2 - 75 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set MOVXB xadr16, obj obj (transfer data memory to external memory) For no post-increment: [HL], [XY], E:[HL], E:[XY] For post-increment: [HL+], [XY+], E:[HL+], E:[XY+] Function (cadr16) 3~0 obj (cadr16) 7~4 obj (for post-increment) HL HL + 2 or XY XY + 2 Description This instruction transfers external memory. Data in the data memory specified by obj is byte-transferred to external memory specified by xadr16. Data memory specified by obj is transferred to bits 3 through 0 of external memory, and data memory specified by obj+1 is transferred to external memory bits 7 to 4. For post-increment operations, the HL or XY register is incremented by 2 after execution. Flags Flags affected by execution of this instruction Flag change conditions (for post-increment) if HL + 2 > 0FFH or XY + 2 > 0FFH then G 1 else G 0 Codes/Cycles Operand xadr16, [HL] xadr16, [XY] xadr16, E:[HL] xadr16, E:[XY] xadr16, [HL+] xadr16, [XY+] xadr16, E:[HL+] xadr16, E:[XY+] Instruction Code 15 0 a15 0 a15 0 a15 0 a15 0 a15 0 a15 0 a15 0 a15 14 0 a14 0 a14 0 a14 0 a14 0 a14 0 a14 0 a14 0 a14 13 0 a13 0 a13 0 a13 0 a13 0 a13 0 a13 0 a13 0 a13 12 0 a12 0 a12 0 a12 0 a12 0 a12 0 a12 0 a12 0 a12 11 0 a11 0 a11 0 a11 0 a11 0 a11 0 a11 0 a11 0 a11 10 0 a10 0 a10 0 a10 0 a10 0 a10 0 a10 0 a10 0 a10 9 1 a9 1 a9 1 a9 1 a9 1 a9 1 a9 1 a9 1 a9 8 1 a8 1 a8 1 a8 1 a8 1 a8 1 a8 1 a8 1 a8 7 1 a7 1 a7 1 a7 1 a7 1 a7 1 a7 1 a7 1 a7 6 1 a6 1 a6 1 a6 1 a6 1 a6 1 a6 1 a6 1 a6 5 1 a5 1 a5 0 a5 0 a5 1 a5 1 a5 0 a5 0 a5 4 0 a4 1 a4 0 a4 1 a4 0 a4 1 a4 0 a4 1 a4 3 0 a3 0 a3 0 a3 0 a3 1 a3 1 a3 1 a3 1 a3 2 0 a2 0 a2 0 a2 0 a2 0 a2 0 a2 0 a2 0 a2 1 0 a1 0 a1 0 a1 0 a1 0 a1 0 a1 0 a1 0 a1 0 1 a0 1 a0 1 a0 1 a0 1 a0 1 a0 1 a0 1 a0 Machine Cycle 3 3 3 3 3 3 3 3 Z C G -- -- m 2 - 76 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set MSA cadr16 Function Melody Start Description (start melody output) Starts melody output from the head address of melody data specified by a15 to a0. Codes/Cycles Operand cadr16 Instruction Code 15 14 13 12 11 10 0 0 0 0 0 0 9 0 8 0 a8 7 0 a7 6 0 a6 5 0 a5 4 1 a4 3 0 a3 2 1 a2 1 1 a1 Machine Cycle 0 0 a0 3 a15 a14 a13 a12 a11 a10 a9 2 - 77 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set MSET obj, #m obj For no post-increment: cur, [HL], [XY], E:[HL], E:[XY] For post-increment: [HL+], [XY+], E:[HL+], E:[XY+] Function Bits not masked by obj 1, A obj (m = 0 ~ 0FH) (for post-increment) HL HL + 1 or XY XY + 1 Description (data memory bit set) Sets all bits not masked by immediate data m, in the data memory specified by obj. After the clear operation the content of obj is stored to the accumulator. m is a value in the range 0 to 0FH, with a "0" masking a bit and a "1" marking a bit to be set. For post-increment operations, the HL or XY register is incremented after execution. Flags Flags affected by execution of this instruction Flag change conditions (for post-increment) if HL + 1 = 0 or XY + 1 = 0 then G 1 else G 0 Codes/Cycles Operand cur. #m [HL]. #m [XY]. #m E:[HL]. #m E:[XY]. #m [HL+]. #m [XY+]. #m E:[HL+]. #m E:[XY+]. #m Instruction Code 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 1 1 1 1 1 1 1 1 8 0 0 0 0 1 1 1 1 7 0 0 0 0 0 0 0 0 6 r6 1 1 1 1 1 1 1 1 5 r5 1 1 0 0 1 1 0 0 4 r4 0 1 0 1 0 1 0 1 3 r3 2 r2 1 r1 0 r0 m3 m2 m1 m0 r7 Machine Cycle 1 1 1 1 1 1 1 1 1 Z C G m -- m m3 m2 m1 m0 m3 m2 m1 m0 m3 m2 m1 m0 m3 m2 m1 m0 m3 m2 m1 m0 m3 m2 m1 m0 m3 m2 m1 m0 m3 m2 m1 m0 2 - 78 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set MTST obj, A obj For no post-increment: sfr, cur, [HL], [XY], E:[HL], E:[XY] For post-increment: [HL+], [XY+], E:[HL+], E:[XY+] Function If any of the bits not masked by A is "0", then Z 1 else Z 0 (for post-increment) HL HL + 1 or XY XY + 1 Description (data memory bit test) Tests all bits not masked by accumulator in the data memory specified by obj. If even one bit is "0", sets the Z flag. In the accumulator a "0" masks a bit and a "1" marks a bit to be tested. For post-increment operations, the HL or XY register is incremented after execution. Flags Flags affected by execution of this instruction Flag change conditions See function column (for post-increment) if HL + 1 = 0 or XY + 1 = 0 then G 1 else G 0 Codes/Cycles Operand sfr, A cur, A [HL], A [XY], A E:[HL], A E:[XY], A [HL+], A [XY+], A E:[HL+], A E:[XY+], A Instruction Code 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 9 1 1 0 0 0 0 0 0 0 0 8 1 1 0 0 0 0 0 0 0 0 7 r7 r7 0 0 0 0 0 0 0 0 6 r6 r6 0 0 0 0 0 0 0 0 5 r5 r5 1 1 0 0 1 1 0 0 4 r4 r4 0 1 0 1 0 1 0 1 3 r3 r3 0 0 0 0 1 1 1 1 2 r2 r2 1 1 1 1 1 1 1 1 1 r1 r1 0 0 0 0 0 0 0 0 0 r0 r0 1 1 1 1 1 1 1 1 Machine Cycle 1 1 1 1 1 1 1 1 1 1 Z C G m -- m 2 - 79 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set MTST obj, #m obj For no post-increment: cur, [HL], [XY], E:[HL], E:[XY] For post-increment: [HL+], [XY+], E:[HL+], E:[XY+] Function If any of the bits not masked by m is "0", then Z 1 else Z 0 (for post-increment) HL HL + 1 or XY XY + 1 Description (data memory bit test) Tests all bits not masked by immediate data m in the data memory specified by obj. If even one bit is "0", sets the Z flag. m is a value from 0 to 0FH, with a "0" masking a bit and a "1" marking a bit to be tested. For post-increment operations, the HL or XY register is incremented after execution. Flags Flags affected by execution of this instruction Flag change conditions See function column (for post-increment) if HL + 1 = 0 or XY + 1 = 0 then G 1 else G 0 Codes/Cycles Operand cur. #m [HL]. #m [XY]. #m E:[HL]. #m E:[XY]. #m [HL+]. #m [XY+]. #m E:[HL+]. #m E:[XY+]. #m Instruction Code 15 14 13 12 11 10 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 9 0 0 0 0 0 0 0 0 8 0 0 0 0 1 1 1 1 7 1 1 1 1 1 1 1 1 6 r6 0 0 0 0 0 0 0 0 5 r5 1 1 0 0 1 1 0 0 4 r4 0 1 0 1 0 1 0 1 3 r3 2 r2 1 r1 0 r0 m3 m2 m1 m0 r7 Machine Cycle 1 1 1 1 1 1 1 1 1 Z C G m -- m m3 m2 m1 m0 m3 m2 m1 m0 m3 m2 m1 m0 m3 m2 m1 m0 m3 m2 m1 m0 m3 m2 m1 m0 m3 m2 m1 m0 m3 m2 m1 m0 2 - 80 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set NOP Function No Operation Description Do nothing for one machine cycle. Codes/Cycles Operand NOP Instruction Code 15 14 13 12 11 10 0 0 0 0 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 (no operation) 0 0 Machine Cycle 1 2 - 81 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set OR obj, A obj (logical add of data memory and accumulator) For no post-increment: sfr, cur, [HL], [XY], E:[HL], E:[XY] For post-increment: [HL+], [XY+], E:[HL+], E:[XY+] Function obj, A obj A (for post-increment) HL HL + 1 or XY XY + 1 Description Takes the logical add for the accumulator and the data memory specified by obj. Results are written to data memory and the accumulator. For post-increment operations, the HL or XY register is incremented after execution. Flags Flags affected by execution of this instruction Flag change conditions if obj A = 0 then Z 1 else Z 0 (for post-increment) if HL + 1 = 0 or XY + 1 = 0 then G 1 else G 0 Codes/Cycles Operand sfr, A cur, A [HL], A [XY], A E:[HL], A E:[XY], A [HL+], A [XY+], A E:[HL+], A E:[XY+], A Instruction Code 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 9 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 0 0 0 0 0 0 7 r7 r7 0 0 0 0 0 0 0 0 6 r6 r6 0 0 0 0 0 0 0 0 5 r5 r5 1 1 0 0 1 1 0 0 4 r4 r4 0 1 0 1 0 1 0 1 3 r3 r3 0 0 0 0 1 1 1 1 2 r2 r2 0 0 0 0 0 0 0 0 1 r1 r1 1 1 1 1 1 1 1 1 Machine Cycle 0 r0 r0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 Z C G m -- m 2 - 82 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set OR obj, #i4 obj (logical add of data memory and immediate data) For no post-increment: cur, [HL], [XY], E:[HL], E:[XY] For post-increment: [HL+], [XY+], E:[HL+], E:[XY+] Function obj, A obj i4 (for post-increment) HL HL + 1 or XY XY + 1 Description Takes the logical add for the immediate data and the data memory specified by obj. Results are written to data memory and the accumulator. For post-increment operations, the HL or XY register is incremented after execution. Flags Flags affected by execution of this instruction Flag change conditions if obj i4 = 0 then Z 1 else Z 0 (for post-increment) if HL + 1 = 0 or XY + 1 = 0 then G 1 else G 0 Codes/Cycles Operand cur, #i4 [HL], #i4 [XY], #i4 E:[HL], #i4 E:[XY], #i4 [HL+], #i4 [XY+], #i4 E:[HL+], #i4 E:[XY+], #i4 Instruction Code 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i3 0 0 0 0 0 0 0 0 i2 0 0 0 0 0 0 0 0 9 i1 1 1 1 1 1 1 1 1 8 i0 0 0 0 0 1 1 1 1 7 r7 0 0 0 0 0 0 0 0 6 r6 1 1 1 1 1 1 1 1 5 r5 1 1 0 0 1 1 0 0 4 r4 0 1 0 1 0 1 0 1 3 r3 i3 i3 i3 i3 i3 i3 i3 i3 2 r2 i2 i2 i2 i2 i2 i2 i2 i2 1 r1 i1 i1 i1 i1 i1 i1 i1 i1 Machine Cycle 0 r0 i0 i0 i0 i0 i0 i0 i0 i0 1 1 1 1 1 1 1 1 1 Z C G m -- m 2 - 83 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set POP HL Function (restores flag registers, accumulator and HL register) RSP RSP - 1, {FLAG, A, HL} (RSP) Description Decrements the register stack pointer, then restores the register stack content to the flag registers (G, C, Z), accumulator and HL register. Flags Flags affected by execution of this instruction Flag change conditions if Z = 1 when PUSH HL executed, then Z 1 else Z 0 if C = 1 when PUSH HL executed then C 1 else C 0 if G = 1 when PUSH HL executed then G 1 else G 0 Codes/Cycles Operand HL Instruction Code 15 14 13 12 11 10 0 0 0 0 0 0 9 0 8 0 7 0 6 0 5 0 4 1 3 0 2 0 1 1 0 0 Machine Cycle 2 Z C G m m m 2 - 84 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set POP XY Function (restores extra bank register, current bank register and XY register) RSP RSP-1, {EBR, CBR, XY} (RSP) Description Decrements the register stack pointer, then restores the register bank stack content to the extra bank register, current bank register and XY register. Flags Flags affected by execution of this instruction Z C G -- Codes/Cycles Operand XY Instruction Code 15 14 13 12 11 10 0 0 0 0 0 0 9 0 8 0 7 0 6 0 5 0 4 1 3 0 2 0 1 1 -- -- 0 1 Machine Cycle 2 PUSH HL Function (saves flag registers, accumulator and HL register) (RSP) (FLAG, A, HL), RSP RSP + 1 Description Saves the flag registers (G, C, Z), accumulator and HL register to the register stack, then increments the register stack pointer. Flags Flags affected by execution of this instruction Z C G -- Codes/Cycles Operand HL Instruction Code 15 14 13 12 11 10 0 0 0 0 0 0 9 0 8 0 7 0 6 0 5 0 4 1 3 0 2 0 1 0 -- -- 0 0 Machine Cycle 2 2 - 85 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set PUSH XY Function (saves extra bank register, current bank register and XY register) (RSP) {EBR, CBR, XY}, RSP RSP + 1 Description Saves the extra bank register, current bank register and XY register to the register stack, then increments the register stack pointer. Flags Flags affected by execution of this instruction Z C G -- Codes/Cycles Operand XY Instruction Code 15 14 13 12 11 10 0 0 0 0 0 0 9 0 8 0 7 0 6 0 5 0 4 1 3 0 2 0 1 0 -- -- 0 1 Machine Cycle 2 2 - 86 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set ROL obj obj For no post-increment: sfr, cur, [HL], [XY], E:[HL], E:[XY] For post-increment: [HL+], [XY+], E:[HL+], E:[XY+] Function obj3 obj2 obj1 obj0 C , A obj (for post-increment) HL HL + 1 or XY XY + 1 Description (rotate left) Rotates the data memory content specified by obj one bit left. The carry flag is stored to data memory LSB, and the MSB to the carry flag. After rotation the data memory content is stored to the accumulator. For post-increment operations, the HL or XY register is incremented after execution. Flags Flags affected by execution of this instruction Flag change conditions if obj3 = 1 (obj bit 3 = 1 before instruction execution) then C 1 else C 0 if A = 0 then Z 1 else Z 0 (for post-increment) if HL + 1 = 0 or XY + 1 = 0 then G 1 else G 0 Codes/Cycles Operand sfr cur [HL] [XY] E:[HL] E:[XY] [HL+] [XY+] E:[HL+] E:[XY+] Instruction Code 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 9 1 1 0 0 0 0 0 0 0 0 8 0 0 0 0 0 0 0 0 0 0 7 r7 r7 0 0 0 0 0 0 0 0 6 r6 r6 0 0 0 0 0 0 0 0 5 r5 r5 1 1 0 0 1 1 0 0 4 r4 r4 0 1 0 1 0 1 0 1 3 r3 r3 0 0 0 0 1 1 1 1 2 r2 r2 1 1 1 1 1 1 1 1 1 r1 r1 1 1 1 1 1 1 1 1 Machine Cycle 0 r0 r0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 Z C G m m m 2 - 87 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set ROR obj obj For no post-increment: sfr, cur, [HL], [XY], E:[HL], E:[XY] For post-increment: [HL+], [XY+], E:[HL+], E:[XY+] Function AE obj3 AE obj2 AE obj1 AE obj0 AE C (for post-increment) HL HL + 1 or XY XY + 1 Description ,A obj (rotate right) Rotates the data memory content specified by obj one bit right. The carry flag is stored to data memory MSB, and the LSB to the carry flag. After rotation the data memory content is stored to the accumulator. For post-increment operations, the HL or XY register is incremented after execution. Flags Flags affected by execution of this instruction Flag change conditions if obj0 = 1 (obj bit 0 = 1 before instruction execution) then C 1 else C 0 if A = 0 then Z 1 else Z 0 (for post-increment) if HL + 1 = 0 or XY + 1 = 0 then G 1 else G 0 Codes/Cycles Operand sfr cur [HL] [XY] E:[HL] E:[XY] [HL+] [XY+] E:[HL+] E:[XY+] Instruction Code 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 9 1 1 0 0 0 0 0 0 0 0 8 1 1 0 0 0 0 0 0 0 0 7 r7 r7 0 0 0 0 0 0 0 0 6 r6 r6 0 0 0 0 0 0 0 0 5 r5 r5 1 1 0 0 1 1 0 0 4 r4 r4 0 1 0 1 0 1 0 1 3 r3 r3 0 0 0 0 1 1 1 1 2 r2 r2 1 1 1 1 1 1 1 1 1 r1 r1 1 1 1 1 1 1 1 1 0 r0 r0 1 1 1 1 1 1 1 1 Machine Cycle 1 1 1 1 1 1 1 1 1 1 Z C G m m m 2 - 88 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set RT Function PC (SP) + 1, SP SP-1 Description (return from subroutine) The PC (program counter) value saved to the call stack by the CAL or LCAL instruction is incremented by one then set to the PC. The call stack pointer is then decremented. Codes/Cycles Operand RT Instruction Code 15 14 13 12 11 10 0 0 0 0 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 1 2 0 1 1 0 1 Machine Cycle 1 RTI Function (return from maskable interrupt processing routine) PC (SP) + 1, SP SP-1, MIE 1 Description The PC (program counter) value saved to the call stack when a maskable interrupt was generated is incremented by one then set to the PC. The call stack pointer is then decremented. MIE is set to 1 to enable maskable interrupts again. The RTI instruction is used as the instruction to return from a maskable interrupt routine. Codes/Cycles Operand RTI Instruction Code 15 14 13 12 11 10 0 0 0 0 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 1 2 1 1 0 0 0 Machine Cycle 1 2 - 89 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set RTNMI Function (return from non-maskable interrupt processing routine) PC (SP) + 1, SP SP-1, MIE Pre-interrupt MIE state Description The PC (program counter) value saved to the call stack when a non-maskable interrupt was generated is incremented by one then set to the PC. The call stack pointer is then decremented. The pre-interrupt state is reset in MIE. The RTNMI instruction is used as the instruction to return from a non-maskable interrupt routine. Codes/Cycles Operand RTNMI Instruction Code 15 14 13 12 11 10 0 0 0 0 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 1 2 1 1 0 0 1 Machine Cycle 1 2 - 90 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set SBC obj, A obj (data memory and accumulator subtraction with carry) For no post-increment: sfr, cur, [HL], [XY], E:[HL], E:[XY] For post-increment: [HL+], [XY+], E:[HL+], E:[XY+] Function obj A obj - A - C (for post-increment) HL HL + 1 or XY XY + 1 Description The accumulator and carry flag are subtracted from the data memory specified by obj, and the results stored to data memory and the accumulator. For post-increment operations, the HL or XY register is incremented after execution. Flags Flags affected by execution of this instruction Flag change conditions if obj - A - C = 0 then Z 1 else Z 0 if obj - A - C < 0 then C 1 else C 0 (for post-increment) if HL + 1 = 0 or XY + 1 = 0 then G 1 else G 0 Codes/Cycles Operand sfr, A cur, A [HL], A [XY], A E:[HL], A E:[XY], A [HL+], A [XY+], A E:[HL+], A E:[XY+], A Instruction Code 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 9 0 0 0 0 0 0 0 0 0 0 8 0 0 1 1 1 1 1 1 1 1 7 r7 r7 0 0 0 0 0 0 0 0 6 r6 r6 0 0 0 0 0 0 0 0 5 r5 r5 1 1 0 0 1 1 0 0 4 r4 r4 0 1 0 1 0 1 0 1 3 r3 r3 0 0 0 0 1 1 1 1 2 r2 r2 1 1 1 1 1 1 1 1 1 r1 r1 1 1 1 1 1 1 1 1 0 r0 r0 0 0 0 0 0 0 0 0 Machine Cycle 1 1 1 1 1 1 1 1 1 1 Z C G m m m 2 - 91 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set SBCD obj, A obj (data memory and accumulator subtraction with carry with decimal adjust) For no post-increment: sfr, cur, [HL], [XY], E:[HL], E:[XY] For post-increment: [HL+], [XY+], E:[HL+], E:[XY+] Function obj, A decimal adjust {obj - A - C} (for post-increment) HL HL + 1 or XY XY + 1 Description The accumulator and carry flag are subtracted from the data memory specified by obj, and the results stored to data memory and the accumulator if there is no resulting borrow. If there is a borrow, the decimal adjustment AH is added and the results stored to data memory and the accumulator. For post-increment operations, the HL or XY register is incremented after execution. Flags Flags affected by execution of this instruction Flag change conditions if the decimal adjustment = 0 then Z 1 else Z 0 if a borrow results, C 1, else C 0 (for post-increment) if HL + 1 = 0 or XY + 1 = 0 then G 1 else G 0 Codes/Cycles Operand sfr, A cur, A [HL], A [XY], A E:[HL], A E:[XY], A [HL+], A [XY+], A E:[HL+], A E:[XY+], A Instruction Code 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 9 0 0 0 0 0 0 0 0 0 0 8 1 1 1 1 1 1 1 1 1 1 7 r7 r7 0 0 0 0 0 0 0 0 6 r6 r6 0 0 0 0 0 0 0 0 5 r5 r5 1 1 0 0 1 1 0 0 4 r4 r4 0 1 0 1 0 1 0 1 3 r3 r3 0 0 0 0 1 1 1 1 2 r2 r2 1 1 1 1 1 1 1 1 1 r1 r1 1 1 1 1 1 1 1 1 0 r0 r0 1 1 1 1 1 1 1 1 Machine Cycle 1 1 1 1 1 1 1 1 1 1 Z C G m m m 2 - 92 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set SBCJ obj, n obj (data memory subtraction with carry with base-n adjust) For no post-increment: cur, [HL], [XY], E:[HL], E:[XY] For post-increment: [HL+], [XY+], E:[HL+], E:[XY+] Function obj, A n adjust {obj-C} (Even number from 2 to 16) (for post-increment) HL HL + 1 or XY XY + 1 Description The accumulator and carry flag are subtracted from the data memory specified by obj, and base-n adjustment completed. The results are stored to data memory and the accumulator. If the result of base-n adjustment is 0FH, the adjustment n is added. n is an even value from 2 to 16. For post-increment operations, the HL or XY register is incremented after execution. Flags Flags affected by execution of this instruction Flag change conditions if the base-n adjustment = 0 then Z 1 else Z 0 if an underflow results, C 1, else C 0 (for post-increment) if HL + 1 = 0 or XY + 1 = 0 then G 1 else G 0 Codes/Cycles Operand cur. n [HL]. n [XY]. n E:[HL]. n E:[XY]. n [HL+]. n [XY+]. n E:[HL+]. n E:[XY+]. n Instruction Code 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 n2 1 1 1 1 1 1 1 1 9 n1 1 1 1 1 1 1 1 1 8 n0 0 0 0 0 1 1 1 1 7 r7 0 0 0 0 0 0 0 0 6 r6 0 0 0 0 0 0 0 0 5 r5 1 1 0 0 1 1 0 0 4 r4 0 1 0 1 0 1 0 1 3 r3 1 1 1 1 1 1 1 1 2 r2 n2 n2 n2 n2 n2 n2 n2 n2 1 r1 n1 n1 n1 n1 n1 n1 n1 n1 0 r0 n0 n0 n0 n0 n0 n0 n0 n0 Machine Cycle 1 1 1 1 1 1 1 1 1 Z C G m m m [Note] The relation between adjustment n and n2 to n0 in the instruction code is shown below. Adjustment n n2 to n0 in instruction code 2 1H 4 2H 6 3H 8 4H 10 5H 12 6H 14 7H 16 0H 2 - 93 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set SJMP radr8 Function PC NextPC + radr8 (However, -128 radr8 +127 Next PC is the address (PC+1) after the instruction) Description (PC relative branch) The content of radr8 is added to NextPC and the program branched. The destination is a range from -128 to +127 from the NextPC address. The 8 bits in the instruction code (a7 to a0) correspond to radr8, and a7 (8th bit) is the sign indicating the direction of displacement from the next address. Branches across program memory page boundaries are possible. The Assembler can directly specify addresses within branch range (labels) instead of radr8. Flags Flags affected by execution of this instruction Z C G -- Codes/Cycles Operand radr8 Instruction Code 15 14 13 12 11 10 0 0 0 0 1 0 9 0 8 a7 7 1 6 a6 5 a5 4 a4 3 a3 2 a2 1 a1 -- -- 0 a0 Machine Cycle 1 2 - 94 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set SUB obj, A obj (data memory and accumulator subtraction) For no post-increment: sfr, cur, [HL], [XY], E:[HL], E:[XY] For post-increment: [HL+], [XY+], E:[HL+], E:[XY+] Function obj, A obj - A (for post-increment) HL HL + 1 or XY XY + 1 Description The accumulator is subtracted from the data memory specified by obj, and the results stored to data memory and the accumulator. For post-increment operations, the HL or XY register is incremented after execution. Flags Flags affected by execution of this instruction Flag change conditions if obj - A = 0 then Z 1 else Z 0 if obj - A < 0 then C 1 else C 0 (for post-increment) if HL + 1 = 0 or XY + 1 = 0 then G 1 else G 0 Codes/Cycles Operand sfr, A cur, A [HL], A [XY], A E:[HL], A E:[XY], A [HL+], A [XY+], A E:[HL+], A E:[XY+], A Instruction Code 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 9 1 1 0 0 0 0 0 0 0 0 8 1 1 1 1 1 1 1 1 1 1 7 r7 r7 0 0 0 0 0 0 0 0 6 r6 r6 0 0 0 0 0 0 0 0 5 r5 r5 1 1 0 0 1 1 0 0 4 r4 r4 0 1 0 1 0 1 0 1 3 r3 r3 0 0 0 0 1 1 1 1 2 r2 r2 1 1 1 1 1 1 1 1 1 r1 r1 0 0 0 0 0 0 0 0 0 r0 r0 1 1 1 1 1 1 1 1 Machine Cycle 1 1 1 1 1 1 1 1 1 1 Z C G m m m 2 - 95 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set SUB obj, #i4 obj (data memory and immediate data subtraction) For no post-increment: cur, [HL], [XY], E:[HL], E:[XY] For post-increment: [HL+], [XY+], E:[HL+], E:[XY+] Function obj, A obj - i4 (for post-increment) HL HL + 1 or XY XY + 1 Description The immediate data i4 is subtracted from the data memory specified by obj, and the results stored to data memory and the accumulator. For post-increment operations, the HL or XY register is incremented after execution. Flags Flags affected by execution of this instruction Flag change conditions if obj - i4 = 0 then Z 1 else Z 0 if obj - i4 < 0 then C 1 else C 0 (for post-increment) if HL + 1 = 0 or XY + 1 = 0 then G 1 else G 0 Codes/Cycles Operand cur, #i4 [HL], #i4 [XY], #i4 E:[HL], #i4 E:[XY], #i4 [HL+], #i4 [XY+], #i4 E:[HL+], #i4 E:[XY+], #i4 Instruction Code 15 14 13 12 11 10 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 i3 0 0 0 0 0 0 0 0 i2 0 0 0 0 0 0 0 0 9 i1 1 1 1 1 1 1 1 1 8 i0 0 0 0 0 1 1 1 1 7 r7 1 1 1 1 1 1 1 1 6 r6 0 0 0 0 0 0 0 0 5 r5 1 1 0 0 1 1 0 0 4 r4 0 1 0 1 0 1 0 1 3 r3 i3 i3 i3 i3 i3 i3 i3 i3 2 r2 i2 i2 i2 i2 i2 i2 i2 i2 1 r1 i1 i1 i1 i1 i1 i1 i1 i1 0 r0 i0 i0 i0 i0 i0 i0 i0 i0 Machine Cycle 1 1 1 1 1 1 1 1 1 Z C G m m m 2 - 96 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set XCH A, obj obj (swap data memory and accumulator contents) For no post-increment: sfr, cur, [HL], [XY], E:[HL], E:[XY] For post-increment: [HL+], [XY+], E:[HL+], E:[XY+] Function A obj (for post-increment) HL HL + 1 or XY XY + 1 Description The accumulator is swapped with the data memory specified by obj. For postincrement operations, the HL or XY register is incremented after execution. Flags Flags affected by execution of this instruction Flag change conditions (for post-increment) if HL + 1 = 0 or XY + 1 = 0 then G 1 else G 0 Codes/Cycles Operand A, sfr A, cur A, [HL] A, [XY] A, E:[HL] A, E:[XY] A, [HL+] A, [XY+] A, E:[HL+] A, E:[XY+] Instruction Code 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 9 1 1 1 1 1 1 1 1 1 1 8 0 0 1 1 1 1 1 1 1 1 7 r7 r7 0 0 0 0 0 0 0 0 6 r6 r6 0 0 0 0 0 0 0 0 5 r5 r5 1 1 0 0 1 1 0 0 4 r4 r4 0 1 0 1 0 1 0 1 3 r3 r3 0 0 0 0 1 1 1 1 2 r2 r2 0 0 0 0 0 0 0 0 1 r1 r1 0 0 0 0 0 0 0 0 0 r0 r0 1 1 1 1 1 1 1 1 Machine Cycle 1 1 1 1 1 1 1 1 1 1 Z C G -- -- m 2 - 97 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set XOR obj, A obj (exclusive OR of data memory and accumulator) For no post-increment: sfr, cur, [HL], [XY], E:[HL], E:[XY] For post-increment: [HL+], [XY+], E:[HL+], E:[XY+] Function obj, A obj " A (for post-increment) HL HL + 1 or XY XY + 1 Description A exclusive OR is executed for the accumulator and the data memory specified by obj, and the results written to data memory and the accumulator. For post-increment operations, the HL or XY register is incremented after execution. Flags Flags affected by execution of this instruction Flag change conditions if obj " A = 0 then Z 1 else Z 0 (for post-increment) if HL + 1 = 0 or XY + 1 = 0 then G 1 else G 0 Codes/Cycles Operand sfr, A cur, A [HL], A [XY], A E:[HL], A E:[XY], A [HL+], A [XY+], A E:[HL+], A E:[XY+], A Instruction Code 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 9 0 0 0 0 0 0 0 0 0 0 8 1 1 0 0 0 0 0 0 0 0 7 r7 r7 0 0 0 0 0 0 0 0 6 r6 r6 0 0 0 0 0 0 0 0 5 r5 r5 1 1 0 0 1 1 0 0 4 r4 r4 0 1 0 1 0 1 0 1 3 r3 r3 0 0 0 0 1 1 1 1 2 r2 r2 0 0 0 0 0 0 0 0 1 r1 r1 1 1 1 1 1 1 1 1 Machine Cycle 0 r0 r0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Z C G m -- m 2 - 98 nX-4/250/300 Core Instruction Manual Chapter 2 Instruction set XOR obj, #i4 obj (exclusive OR of data memory and immediate data) For no post-increment: cur, [HL], [XY], E:[HL], E:[XY] For post-increment: [HL+], [XY+], E:[HL+], E:[XY+] Function obj, A obj " i4 (for post-increment) HL HL + 1 or XY XY + 1 Description A exclusive OR is executed for the immediate data and the data memory specified by obj, and the results written to data memory and the accumulator. For post-increment operations, the HL or XY register is incremented after execution. Flags Flags affected by execution of this instruction Flag change conditions if obj " i4 = 0 then Z 1 else Z 0 (for post-increment) if HL + 1 = 0 or XY + 1 = 0 then G 1 else G 0 Codes/Cycles Operand cur, #i4 [HL], #i4 [XY], #i4 E:[HL], #i4 E:[XY], #i4 [HL+], #i4 [XY+], #i4 E:[HL+], #i4 E:[XY+], #i4 Instruction Code 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 i3 0 0 0 0 0 0 0 0 i2 0 0 0 0 0 0 0 0 9 i1 0 0 0 0 0 0 0 0 8 i0 0 0 0 0 1 1 1 1 7 r7 0 0 0 0 0 0 0 0 6 r6 1 1 1 1 1 1 1 1 5 r5 1 1 0 0 1 1 0 0 4 r4 0 1 0 1 0 1 0 1 3 r3 i3 i3 i3 i3 i3 i3 i3 i3 2 r2 i2 i2 i2 i2 i2 i2 i2 i2 1 r1 i1 i1 i1 i1 i1 i1 i1 i1 Machine Cycle 0 r0 i0 i0 i0 i0 i0 i0 i0 i0 1 1 1 1 1 1 1 1 1 Z C G m -- m 2 - 99 |
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